24 static struct ccsr_rcpm_v2 __iomem *rcpm_v2_regs;  variable
43 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
44 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
45 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
46 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
65 	clrbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_unmask()
66 	clrbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_unmask()
67 	clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_unmask()
68 	clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_unmask()
82 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
84 		clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
113 		setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);  in rcpm_v2_cpu_enter_state()
116 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
119 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
122 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
195 		setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);  in rcpm_v2_cpu_exit_state()
198 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
201 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
204 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
245 	u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;  in rcpm_v2_plat_enter_state()
306 	rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);  in rcpm_v2_freeze_time_base()
374 	rcpm_v2_regs = base;  in fsl_rcpm_init()