77 #define HAMMERHEAD_BASE		0xf8000000
78 #define HHEAD_CONFIG		0x90
79 #define HHEAD_SEC_INTR		0xc0
83 #define PSURGE_PRI_INTR		0xf3019000
87 #define PSURGE_START		0xf2800000
90 #define PSURGE_QUAD_REG_ADDR	0xf8800000
92 #define PSURGE_QUAD_IRQ_SET	0
103 #define PSURGE_QUAD_IN(r)	(in_8(quad_base + ((r) << 4) + 4) & 0x0f)
116 #define PSURGE_DUAL		0
135 	if (cpu == 0)  in psurge_set_ipi()
138 		out_8(psurge_sec_intr, 0);  in psurge_set_ipi()
145 	if (cpu > 0) {  in psurge_clr_ipi()
148 			out_8(psurge_sec_intr, ~0);  in psurge_clr_ipi()
182 	return 0;  in psurge_host_map()
193 	psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL);  in psurge_secondary_ipi_init()
226 	for (i = 0; i < 100; i++) {  in psurge_quad_probe()
228 		bogus[(0+i)%8] = 0x00000000;  in psurge_quad_probe()
229 		bogus[(1+i)%8] = 0x55555555;  in psurge_quad_probe()
230 		bogus[(2+i)%8] = 0xFFFFFFFF;  in psurge_quad_probe()
231 		bogus[(3+i)%8] = 0xAAAAAAAA;  in psurge_quad_probe()
232 		bogus[(4+i)%8] = 0x33333333;  in psurge_quad_probe()
233 		bogus[(5+i)%8] = 0xCCCCCCCC;  in psurge_quad_probe()
234 		bogus[(6+i)%8] = 0xCCCCCCCC;  in psurge_quad_probe()
235 		bogus[(7+i)%8] = 0x33333333;  in psurge_quad_probe()
237 		asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");  in psurge_quad_probe()
249 	if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);  in psurge_quad_init()
256 	out_8(psurge_sec_intr, ~0);  in psurge_quad_init()
289 	hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);  in smp_psurge_probe()
303 		if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {  in smp_psurge_probe()
328 	if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);  in smp_psurge_probe()
344 	for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)  in smp_psurge_kick_cpu()
345 		asm volatile("dcbf 0,%0" : : "r" (a) : "memory");  in smp_psurge_kick_cpu()
348 	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);  in smp_psurge_kick_cpu()
361 	for (i = 0; i < 2000; ++i)  in smp_psurge_kick_cpu()
370 	for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {  in smp_psurge_kick_cpu()
382 		tb_req = 0;  in smp_psurge_kick_cpu()
395 	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);  in smp_psurge_kick_cpu()
397 	return 0;  in smp_psurge_kick_cpu()
405 	if (cpu_nr != 0 || !psurge_start)  in smp_psurge_setup_cpu()
410 	out_be32(psurge_start, 0x100);  in smp_psurge_setup_cpu()
426 	set_tb(timebase >> 32, timebase & 0xffffffff);  in smp_psurge_take_timebase()
427 	timebase = 0;  in smp_psurge_take_timebase()
463 	tb_req = 0;  in smp_core99_give_timebase()
471 	(*pmac_tb_freeze)(0);  in smp_core99_give_timebase()
489 	set_tb(timebase >> 32, timebase & 0xffffffff);  in smp_core99_take_timebase()
490 	timebase = 0;  in smp_core99_take_timebase()
508 	/* Strangely, the device-tree says address is 0xd2, but darwin  in smp_core99_cypress_tb_freeze()
509 	 * accesses 0xd0 ...  in smp_core99_cypress_tb_freeze()
514 			   0xd0 | pmac_i2c_read,  in smp_core99_cypress_tb_freeze()
515 			   1, 0x81, &data, 1);  in smp_core99_cypress_tb_freeze()
516 	if (rc != 0)  in smp_core99_cypress_tb_freeze()
519 	data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);  in smp_core99_cypress_tb_freeze()
523 			   0xd0 | pmac_i2c_write,  in smp_core99_cypress_tb_freeze()
524 			   1, 0x81, &data, 1);  in smp_core99_cypress_tb_freeze()
527 	if (rc != 0) {  in smp_core99_cypress_tb_freeze()
544 			   1, 0x2e, &data, 1);  in smp_core99_pulsar_tb_freeze()
545 	if (rc != 0)  in smp_core99_pulsar_tb_freeze()
548 	data = (data & 0x88) | (freeze ? 0x11 : 0x22);  in smp_core99_pulsar_tb_freeze()
553 			   1, 0x2e, &data, 1);  in smp_core99_pulsar_tb_freeze()
555 	if (rc != 0) {  in smp_core99_pulsar_tb_freeze()
585 		case 0xd2:  in smp_core99_setup_i2c_hwsync()
588 				pmac_tb_pulsar_addr = 0xd2;  in smp_core99_setup_i2c_hwsync()
595 		case 0xd4:  in smp_core99_setup_i2c_hwsync()
597 			pmac_tb_pulsar_addr = 0xd4;  in smp_core99_setup_i2c_hwsync()
634 	args.u[0].v = !freeze;  in smp_core99_pfunc_tb_freeze()
652 		pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);  in smp_core99_gpio_tb_freeze()
653 	pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);  in smp_core99_gpio_tb_freeze()
669 	if (cpu == 0) {  in core99_init_caches()
674 		_set_L2CR(0);  in core99_init_caches()
682 	if (cpu == 0){  in core99_init_caches()
687 		_set_L3CR(0);  in core99_init_caches()
734 		       " GPIO 0x%02x\n", core99_tb_gpio);  in smp_core99_setup()
758 		powersave_nap = 0;  in smp_core99_setup()
764 	int ncpus = 0;  in smp_core99_probe()
766 	if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);  in smp_core99_probe()
790 	/* Collect l2cr and l3cr values from CPU 0 */  in smp_core99_probe()
791 	core99_init_caches(0);  in smp_core99_probe()
798 	unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);  in smp_core99_kick_cpu()
800 	if (nr < 0 || nr > 3)  in smp_core99_kick_cpu()
804 		ppc_md.progress("smp_core99_kick_cpu", 0x346);  in smp_core99_kick_cpu()
818 	pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);  in smp_core99_kick_cpu()
831 	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);  in smp_core99_kick_cpu()
833 	return 0;  in smp_core99_kick_cpu()
839 	if (cpu_nr != 0)  in smp_core99_setup_cpu()
863 	return 0;  in smp_core99_cpu_prepare()
871 		smp_core99_host_open = 0;  in smp_core99_cpu_online()
873 	return 0;  in smp_core99_cpu_online()
900 		ppc_md.progress("smp_core99_bringup_done", 0x349);  in smp_core99_bringup_done()
912 	mpic_cpu_set_priority(0xf);  in smp_core99_cpu_disable()
916 	return 0;  in smp_core99_cpu_disable()
964 		set_dec(0x7fffffff);  in pmac_cpu_offline_self()