Lines Matching refs:hose
140 struct pci_controller *hose; in macrisc_cfg_map_bus() local
142 hose = pci_bus_to_host(bus); in macrisc_cfg_map_bus()
143 if (hose == NULL) in macrisc_cfg_map_bus()
146 if (bus->number == hose->first_busno) { in macrisc_cfg_map_bus()
155 out_le32(hose->cfg_addr, caddr); in macrisc_cfg_map_bus()
156 } while (in_le32(hose->cfg_addr) != caddr); in macrisc_cfg_map_bus()
159 return hose->cfg_data + offset; in macrisc_cfg_map_bus()
204 static void __init setup_chaos(struct pci_controller *hose, in setup_chaos() argument
208 hose->ops = &chaos_pci_ops; in setup_chaos()
209 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_chaos()
210 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_chaos()
229 static int u3_ht_skip_device(struct pci_controller *hose, in u3_ht_skip_device() argument
245 busdn = hose->dn; in u3_ht_skip_device()
270 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, in u3_ht_cfg_access() argument
274 if (bus == hose->first_busno) { in u3_ht_cfg_access()
276 return hose->cfg_data + U3_HT_CFA0(devfn, offset); in u3_ht_cfg_access()
278 return ((void __iomem *)hose->cfg_addr) + (offset << 2); in u3_ht_cfg_access()
280 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); in u3_ht_cfg_access()
286 struct pci_controller *hose; in u3_ht_read_config() local
290 hose = pci_bus_to_host(bus); in u3_ht_read_config()
291 if (hose == NULL) in u3_ht_read_config()
295 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_read_config()
299 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_read_config()
337 struct pci_controller *hose; in u3_ht_write_config() local
341 hose = pci_bus_to_host(bus); in u3_ht_write_config()
342 if (hose == NULL) in u3_ht_write_config()
346 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); in u3_ht_write_config()
350 switch (u3_ht_skip_device(hose, bus, devfn)) { in u3_ht_write_config()
400 struct pci_controller *hose; in u4_pcie_cfg_map_bus() local
406 hose = pci_bus_to_host(bus); in u4_pcie_cfg_map_bus()
407 if (!hose) in u4_pcie_cfg_map_bus()
410 if (bus->number == hose->first_busno) { in u4_pcie_cfg_map_bus()
417 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_map_bus()
418 } while (in_le32(hose->cfg_addr) != caddr); in u4_pcie_cfg_map_bus()
421 return hose->cfg_data + offset; in u4_pcie_cfg_map_bus()
494 struct pci_controller* hose; in init_p2pbridge() local
510 hose = pci_find_hose_for_OF_device(p2pbridge); in init_p2pbridge()
511 if (!hose) { in init_p2pbridge()
515 if (early_read_config_word(hose, bus, devfn, in init_p2pbridge()
522 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); in init_p2pbridge()
540 struct pci_controller* hose = in init_second_ohare() local
542 if (!hose) { in init_second_ohare()
547 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); in init_second_ohare()
550 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); in init_second_ohare()
567 struct pci_controller *hose; in fixup_nec_usb2() local
589 hose = pci_find_hose_for_OF_device(nec); in fixup_nec_usb2()
590 if (!hose) in fixup_nec_usb2()
592 early_read_config_dword(hose, bus, devfn, 0xe4, &data); in fixup_nec_usb2()
597 early_write_config_dword(hose, bus, devfn, 0xe4, data); in fixup_nec_usb2()
602 static void __init setup_bandit(struct pci_controller *hose, in setup_bandit() argument
605 hose->ops = ¯isc_pci_ops; in setup_bandit()
606 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_bandit()
607 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_bandit()
608 init_bandit(hose); in setup_bandit()
611 static int __init setup_uninorth(struct pci_controller *hose, in setup_uninorth() argument
616 hose->ops = ¯isc_pci_ops; in setup_uninorth()
617 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); in setup_uninorth()
618 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); in setup_uninorth()
625 static void __init setup_u3_agp(struct pci_controller* hose) in setup_u3_agp() argument
636 hose->first_busno = 0xf0; in setup_u3_agp()
637 hose->last_busno = 0xff; in setup_u3_agp()
639 hose->ops = ¯isc_pci_ops; in setup_u3_agp()
640 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u3_agp()
641 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u3_agp()
642 u3_agp = hose; in setup_u3_agp()
645 static void __init setup_u4_pcie(struct pci_controller* hose) in setup_u4_pcie() argument
650 hose->ops = &u4_pcie_pci_ops; in setup_u4_pcie()
651 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u4_pcie()
652 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u4_pcie()
660 hose->first_busno = 0x00; in setup_u4_pcie()
661 hose->last_busno = 0xff; in setup_u4_pcie()
664 static void __init parse_region_decode(struct pci_controller *hose, in parse_region_decode() argument
688 hose->mem_resources[cur].flags = IORESOURCE_MEM; in parse_region_decode()
689 hose->mem_resources[cur].name = hose->dn->full_name; in parse_region_decode()
690 hose->mem_resources[cur].start = base; in parse_region_decode()
691 hose->mem_resources[cur].end = end; in parse_region_decode()
692 hose->mem_offset[cur] = 0; in parse_region_decode()
696 hose->mem_resources[cur].end = end; in parse_region_decode()
702 static void __init setup_u3_ht(struct pci_controller* hose) in setup_u3_ht() argument
704 struct device_node *np = hose->dn; in setup_u3_ht()
708 hose->ops = &u3_ht_pci_ops; in setup_u3_ht()
721 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); in setup_u3_ht()
722 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); in setup_u3_ht()
729 hose->io_base_phys = 0xf4000000; in setup_u3_ht()
730 hose->pci_io_size = 0x00400000; in setup_u3_ht()
731 hose->io_resource.name = np->full_name; in setup_u3_ht()
732 hose->io_resource.start = 0; in setup_u3_ht()
733 hose->io_resource.end = 0x003fffff; in setup_u3_ht()
734 hose->io_resource.flags = IORESOURCE_IO; in setup_u3_ht()
735 hose->first_busno = 0; in setup_u3_ht()
736 hose->last_busno = 0xef; in setup_u3_ht()
739 decode = in_be32(hose->cfg_addr + 0x80); in setup_u3_ht()
763 parse_region_decode(hose, decode); in setup_u3_ht()
775 struct pci_controller *hose; in pmac_add_bridge() local
793 hose = pcibios_alloc_controller(dev); in pmac_add_bridge()
794 if (!hose) in pmac_add_bridge()
796 hose->first_busno = bus_range ? bus_range[0] : 0; in pmac_add_bridge()
797 hose->last_busno = bus_range ? bus_range[1] : 0xff; in pmac_add_bridge()
798 hose->controller_ops = pmac_pci_controller_ops; in pmac_add_bridge()
805 setup_u3_agp(hose); in pmac_add_bridge()
809 setup_u3_ht(hose); in pmac_add_bridge()
813 setup_u4_pcie(hose); in pmac_add_bridge()
818 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); in pmac_add_bridge()
824 primary = setup_uninorth(hose, &rsrc); in pmac_add_bridge()
828 setup_grackle(hose); in pmac_add_bridge()
831 setup_bandit(hose, &rsrc); in pmac_add_bridge()
834 setup_chaos(hose, &rsrc); in pmac_add_bridge()
840 disp_name, (unsigned long long)rsrc.start, hose->first_busno, in pmac_add_bridge()
841 hose->last_busno); in pmac_add_bridge()
845 hose, hose->cfg_addr, hose->cfg_data); in pmac_add_bridge()
849 pci_process_bridge_OF_ranges(hose, dev, primary); in pmac_add_bridge()
856 pci_devs_phb_init_dynamic(hose); in pmac_add_bridge()
883 struct pci_controller *hose = pci_bus_to_host(bridge->bus); in pmac_pci_root_bridge_prepare() local
886 if (hose != u3_agp) in pmac_pci_root_bridge_prepare()
894 np = hose->dn; in pmac_pci_root_bridge_prepare()