96 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,  in u3_agp_cfg_access()  argument
101 	if (bus == hose->first_busno) {  in u3_agp_cfg_access()
110 		out_le32(hose->cfg_addr, caddr);  in u3_agp_cfg_access()
111 	} while (in_le32(hose->cfg_addr) != caddr);  in u3_agp_cfg_access()
114 	return hose->cfg_data + offset;  in u3_agp_cfg_access()
120 	struct pci_controller *hose;  in u3_agp_read_config()  local
123 	hose = pci_bus_to_host(bus);  in u3_agp_read_config()
124 	if (hose == NULL)  in u3_agp_read_config()
127 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_read_config()
151 	struct pci_controller *hose;  in u3_agp_write_config()  local
154 	hose = pci_bus_to_host(bus);  in u3_agp_write_config()
155 	if (hose == NULL)  in u3_agp_write_config()
158 	addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);  in u3_agp_write_config()
195 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,  in u3_ht_cfg_access()  argument
198 	if (bus == hose->first_busno) {  in u3_ht_cfg_access()
201 		return hose->cfg_data + u3_ht_cfa0(devfn, offset);  in u3_ht_cfg_access()
203 		return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);  in u3_ht_cfg_access()
206 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_read_config()  argument
211 	addr = hose->cfg_addr;  in u3_ht_root_read_config()
229 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,  in u3_ht_root_write_config()  argument
234 	addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));  in u3_ht_root_write_config()
257 	struct pci_controller *hose;  in u3_ht_read_config()  local
260 	hose = pci_bus_to_host(bus);  in u3_ht_read_config()
261 	if (hose == NULL)  in u3_ht_read_config()
264 	if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))  in u3_ht_read_config()
265 		return u3_ht_root_read_config(hose, offset, len, val);  in u3_ht_read_config()
270 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_read_config()
295 	struct pci_controller *hose;  in u3_ht_write_config()  local
298 	hose = pci_bus_to_host(bus);  in u3_ht_write_config()
299 	if (hose == NULL)  in u3_ht_write_config()
302 	if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))  in u3_ht_write_config()
303 		return u3_ht_root_write_config(hose, offset, len, val);  in u3_ht_write_config()
308 	addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);  in u3_ht_write_config()
352 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,  in u4_pcie_cfg_access()  argument
357         if (bus == hose->first_busno)  in u4_pcie_cfg_access()
364                 out_le32(hose->cfg_addr, caddr);  in u4_pcie_cfg_access()
365         } while (in_le32(hose->cfg_addr) != caddr);  in u4_pcie_cfg_access()
368         return hose->cfg_data + offset;  in u4_pcie_cfg_access()
374         struct pci_controller *hose;  in u4_pcie_read_config()  local
377         hose = pci_bus_to_host(bus);  in u4_pcie_read_config()
378         if (hose == NULL)  in u4_pcie_read_config()
382         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_read_config()
405         struct pci_controller *hose;  in u4_pcie_write_config()  local
408         hose = pci_bus_to_host(bus);  in u4_pcie_write_config()
409         if (hose == NULL)  in u4_pcie_write_config()
413         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);  in u4_pcie_write_config()
440 static void __init setup_u3_agp(struct pci_controller* hose)  in setup_u3_agp()  argument
451 	hose->first_busno = 0xf0;  in setup_u3_agp()
452 	hose->last_busno = 0xff;  in setup_u3_agp()
453 	hose->ops = &u3_agp_pci_ops;  in setup_u3_agp()
454 	hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u3_agp()
455 	hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u3_agp()
457 	u3_agp = hose;  in setup_u3_agp()
460 static void __init setup_u4_pcie(struct pci_controller* hose)  in setup_u4_pcie()  argument
465         hose->ops = &u4_pcie_pci_ops;  in setup_u4_pcie()
466         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);  in setup_u4_pcie()
467         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);  in setup_u4_pcie()
469         u4_pcie = hose;  in setup_u4_pcie()
472 static void __init setup_u3_ht(struct pci_controller* hose)  in setup_u3_ht()  argument
474 	hose->ops = &u3_ht_pci_ops;  in setup_u3_ht()
480 	hose->cfg_data = ioremap(0xf2000000, 0x02000000);  in setup_u3_ht()
481 	hose->cfg_addr = ioremap(0xf8070000, 0x1000);  in setup_u3_ht()
483 	hose->first_busno = 0;  in setup_u3_ht()
484 	hose->last_busno = 0xef;  in setup_u3_ht()
486 	u3_ht = hose;  in setup_u3_ht()
492 	struct pci_controller *hose;  in maple_add_bridge()  local
505 	hose = pcibios_alloc_controller(dev);  in maple_add_bridge()
506 	if (hose == NULL)  in maple_add_bridge()
508 	hose->first_busno = bus_range ? bus_range[0] : 0;  in maple_add_bridge()
509 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in maple_add_bridge()
510 	hose->controller_ops = maple_pci_controller_ops;  in maple_add_bridge()
514 		setup_u3_agp(hose);  in maple_add_bridge()
518 		setup_u3_ht(hose);  in maple_add_bridge()
522                 setup_u4_pcie(hose);  in maple_add_bridge()
527 		disp_name, hose->first_busno, hose->last_busno);  in maple_add_bridge()
531 	pci_process_bridge_OF_ranges(hose, dev, primary);  in maple_add_bridge()
537 	isa_bridge_find_early(hose);  in maple_add_bridge()
540 	pci_devs_phb_init_dynamic(hose);  in maple_add_bridge()
573 	struct pci_controller *hose = pci_bus_to_host(bridge->bus);  in maple_pci_root_bridge_prepare()  local
576 	if (hose != u3_agp)  in maple_pci_root_bridge_prepare()
583 	np = hose->dn;  in maple_pci_root_bridge_prepare()