platforms/chrp/gg2.h

23 #define GG2_PCI_MEM_BASE	0xc0000000	/* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE	0xf7000000	/* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE		0xf8000000	/* Peripheral I/O space */
26 #define GG2_PCI_CONFIG_BASE	0xfec00000	/* PCI configuration space */
27 #define GG2_INT_ACK_SPECIAL	0xfec80000	/* Interrupt acknowledge and */
29 #define GG2_ROM_BASE0		0xff000000	/* ROM bank 0 */
30 #define GG2_ROM_BASE1		0xff800000	/* ROM bank 1 */
39 #define GG2_PCI_BUSNO		0x40	/* Bus number */
40 #define GG2_PCI_SUBBUSNO	0x41	/* Subordinate bus number */
41 #define GG2_PCI_DISCCTR		0x42	/* Disconnect counter */
42 #define GG2_PCI_PPC_CTRL	0x50	/* PowerPC interface control register */
43 #define GG2_PCI_ADDR_MAP	0x5c	/* Address map */
44 #define GG2_PCI_PCI_CTRL	0x60	/* PCI interface control register */
45 #define GG2_PCI_ROM_CTRL	0x70	/* ROM interface control register */
46 #define GG2_PCI_ROM_TIME	0x74	/* ROM timing */
47 #define GG2_PCI_CC_CTRL		0x80	/* Cache controller control register */
48 #define GG2_PCI_DRAM_BANK0	0x90	/* Control register for DRAM bank #0 */
49 #define GG2_PCI_DRAM_BANK1	0x94	/* Control register for DRAM bank #1 */
50 #define GG2_PCI_DRAM_BANK2	0x98	/* Control register for DRAM bank #2 */
51 #define GG2_PCI_DRAM_BANK3	0x9c	/* Control register for DRAM bank #3 */
52 #define GG2_PCI_DRAM_BANK4	0xa0	/* Control register for DRAM bank #4 */
53 #define GG2_PCI_DRAM_BANK5	0xa4	/* Control register for DRAM bank #5 */
54 #define GG2_PCI_DRAM_TIME0	0xb0	/* Timing parameters set #0 */
55 #define GG2_PCI_DRAM_TIME1	0xb4	/* Timing parameters set #1 */
56 #define GG2_PCI_DRAM_CTRL	0xc0	/* DRAM control */
57 #define GG2_PCI_ERR_CTRL	0xd0	/* Error control register */
58 #define GG2_PCI_ERR_STATUS	0xd4	/* Error status register */