282 	unsigned long stat, mask;  in spu_irq_class_0()  local
288 	stat = spu_int_stat_get(spu, 0) & mask;  in spu_irq_class_0()
290 	spu->class_0_pending |= stat;  in spu_irq_class_0()
296 	spu_int_stat_clear(spu, 0, stat);  in spu_irq_class_0()
306 	unsigned long stat, mask, dar, dsisr;  in spu_irq_class_1()  local
313 	stat  = spu_int_stat_get(spu, 1) & mask;  in spu_irq_class_1()
316 	if (stat & CLASS1_STORAGE_FAULT_INTR)  in spu_irq_class_1()
318 	spu_int_stat_clear(spu, 1, stat);  in spu_irq_class_1()
320 	pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,  in spu_irq_class_1()
323 	if (stat & CLASS1_SEGMENT_FAULT_INTR)  in spu_irq_class_1()
326 	if (stat & CLASS1_STORAGE_FAULT_INTR)  in spu_irq_class_1()
334 	return stat ? IRQ_HANDLED : IRQ_NONE;  in spu_irq_class_1()
341 	unsigned long stat;  in spu_irq_class_2()  local
348 	stat = spu_int_stat_get(spu, 2);  in spu_irq_class_2()
351 	stat &= mask;  in spu_irq_class_2()
354 	if (stat & mailbox_intrs)  in spu_irq_class_2()
355 		spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));  in spu_irq_class_2()
357 	spu_int_stat_clear(spu, 2, stat);  in spu_irq_class_2()
359 	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);  in spu_irq_class_2()
361 	if (stat & CLASS2_MAILBOX_INTR)  in spu_irq_class_2()
364 	if (stat & CLASS2_SPU_STOP_INTR)  in spu_irq_class_2()
367 	if (stat & CLASS2_SPU_HALT_INTR)  in spu_irq_class_2()
370 	if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)  in spu_irq_class_2()
373 	if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)  in spu_irq_class_2()
380 	return stat ? IRQ_HANDLED : IRQ_NONE;  in spu_irq_class_2()
659 static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);