41 struct media5200_irq {  struct
46 struct media5200_irq media5200_irq;  variable
53 	spin_lock_irqsave(&media5200_irq.lock, flags);  in media5200_irq_unmask()
54 	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);  in media5200_irq_unmask()
56 	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);  in media5200_irq_unmask()
57 	spin_unlock_irqrestore(&media5200_irq.lock, flags);  in media5200_irq_unmask()
65 	spin_lock_irqsave(&media5200_irq.lock, flags);  in media5200_irq_mask()
66 	val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);  in media5200_irq_mask()
68 	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);  in media5200_irq_mask()
69 	spin_unlock_irqrestore(&media5200_irq.lock, flags);  in media5200_irq_mask()
92 	status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);  in media5200_irq_cascade()
93 	enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);  in media5200_irq_cascade()
96 		generic_handle_domain_irq(media5200_irq.irqhost, val - 1);  in media5200_irq_cascade()
114 	irq_set_chip_data(virq, &media5200_irq);  in media5200_irq_map()
156 	media5200_irq.regs = of_iomap(fpga_np, 0);  in media5200_init_irq()
157 	if (!media5200_irq.regs)  in media5200_init_irq()
159 	pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);  in media5200_init_irq()
167 	out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);  in media5200_init_irq()
169 	spin_lock_init(&media5200_irq.lock);  in media5200_init_irq()
171 	media5200_irq.irqhost = irq_domain_add_linear(fpga_np,  in media5200_init_irq()
172 			MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq);  in media5200_init_irq()
173 	if (!media5200_irq.irqhost)  in media5200_init_irq()
179 	irq_set_handler_data(cascade_virq, &media5200_irq);  in media5200_init_irq()