18 #define PM_PMC_MSK	0xf
20 #define PM_UNIT_MSK	0xf
25 #define PM_PMCSEL_MSK	0xf
28 #define PM_NONE		0
45 #define MMCR_PMCSEL_MSK		0x1f
92  *     48-49: SPCSEL value 0x3_0000_0000_0000
95  *     46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
98  *     44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
101  *     43: UC3 error 0x0800_0000_0000
102  *     42: FPU|IFU|VPU events needed 0x0400_0000_0000
103  *     41: ISU events needed 0x0200_0000_0000
104  *     40: IDU|STS events needed 0x0100_0000_0000
107  *     39: PS1 error 0x0080_0000_0000
108  *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
111  *     35: PS2 error 0x0008_0000_0000
112  *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
115  *     28-31: Byte 0 event source 0xf000_0000
122  *     15: P1 error 0x8000
126  *     0-13: Count of events needing PMC2..PMC8
143  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
155 		if (psel == 0)		/* add events */  in p970_marked_instr_event()
160 			return 0;  in p970_marked_instr_event()
166 	mask = 0;  in p970_marked_instr_event()
169 		mask = 0x4c;		/* byte 0 bits 2,3,6 */  in p970_marked_instr_event()
172 		/* byte 2 bits 0,2,3,4,6; all of byte 1 */  in p970_marked_instr_event()
173 		mask = 0x085dff00;  in p970_marked_instr_event()
176 		mask = 0x50 << 24;	/* byte 3 bits 4,6 */  in p970_marked_instr_event()
184 	[PM_FPU] =   { 0xc80000000000ull, 0x040000000000ull },
185 	[PM_VPU] =   { 0xc80000000000ull, 0xc40000000000ull },
186 	[PM_ISU] =   { 0x080000000000ull, 0x020000000000ull },
187 	[PM_IFU] =   { 0xc80000000000ull, 0x840000000000ull },
188 	[PM_IDU] =   { 0x380000000000ull, 0x010000000000ull },
189 	[PM_STS] =   { 0x380000000000ull, 0x310000000000ull },
196 	unsigned long mask = 0, value = 0;  in p970_get_constraint()
212 		mask |= unit_cons[unit][0];  in p970_get_constraint()
216 		 * Bus events on bytes 0 and 2 can be counted  in p970_get_constraint()
222 		mask  |= 0xfULL << (28 - 4 * byte);  in p970_get_constraint()
225 	if (grp == 0) {  in p970_get_constraint()
227 		mask  |= 0x8000000000ull;  in p970_get_constraint()
228 		value |= 0x1000000000ull;  in p970_get_constraint()
231 		mask  |= 0x800000000ull;  in p970_get_constraint()
232 		value |= 0x100000000ull;  in p970_get_constraint()
241 	return 0;  in p970_get_constraint()
246 	alt[0] = event;  in p970_get_alternatives()
249 	if (event == 0x2002 || event == 0x3002) {  in p970_get_alternatives()
250 		alt[1] = event ^ 0x1000;  in p970_get_alternatives()
262 	unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;  in p970_compute_mmcr()
265 	unsigned int pmc_inuse = 0;  in p970_compute_mmcr()
269 	unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };  in p970_compute_mmcr()
279 	pmc_grp_use[0] = pmc_grp_use[1] = 0;  in p970_compute_mmcr()
280 	memset(busbyte, 0, sizeof(busbyte));  in p970_compute_mmcr()
281 	memset(unituse, 0, sizeof(unituse));  in p970_compute_mmcr()
282 	for (i = 0; i < n_ev; ++i) {  in p970_compute_mmcr()
304 	if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)  in p970_compute_mmcr()
317 	ttmuse[0] = ttmuse[1] = 0;  in p970_compute_mmcr()
326 	if (ttmuse[0] > 1 || ttmuse[1] > 1)  in p970_compute_mmcr()
330 	for (byte = 0; byte < 4; ++byte) {  in p970_compute_mmcr()
348 	memset(pmcsel, 0x8, sizeof(pmcsel));	/* 8 means don't count */  in p970_compute_mmcr()
349 	for (i = 0; i < n_ev; ++i) {  in p970_compute_mmcr()
357 				psel |= 0x10 | ((byte & 2) << 2);  in p970_compute_mmcr()
360 			for (pmc = 0; pmc < 8; ++pmc) {  in p970_compute_mmcr()
376 			if (psel == 0 && (byte & 2))  in p970_compute_mmcr()
387 	for (pmc = 0; pmc < 2; ++pmc)  in p970_compute_mmcr()
394 	if (pmc_inuse & 0xfe)  in p970_compute_mmcr()
397 	mmcra |= 0x2000;	/* mark only one IOP per PPC instruction */  in p970_compute_mmcr()
403 	return 0;  in p970_compute_mmcr()
411 	 * Setting the PMCxSEL field to 0x08 disables PMC x.  in p970_disable_pmc()
415 		mmcr->mmcr0 = (mmcr->mmcr0 & ~(0x1fUL << shift)) | (0x08UL << shift);  in p970_disable_pmc()
418 		mmcr->mmcr1 = (mmcr->mmcr1 & ~(0x1fUL << shift)) | (0x08UL << shift);  in p970_disable_pmc()
425 	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0x8810, /* PM_LD_REF_L1 */
426 	[PERF_COUNT_HW_CACHE_MISSES]		= 0x3810, /* PM_LD_MISS_L1 */
427 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x431,  /* PM_BR_ISSUED */
428 	[PERF_COUNT_HW_BRANCH_MISSES] 		= 0x327,  /* PM_GRP_BR_MPRED */
435  * 0 means not supported, -1 means nonsensical, other values
440 		[C(OP_READ)] = {	0x8810,		0x3810	},
441 		[C(OP_WRITE)] = {	0x7810,		0x813	},
442 		[C(OP_PREFETCH)] = {	0x731,		0	},
445 		[C(OP_READ)] = {	0,		0	},
447 		[C(OP_PREFETCH)] = {	0,		0	},
450 		[C(OP_READ)] = {	0,		0	},
451 		[C(OP_WRITE)] = {	0,		0	},
452 		[C(OP_PREFETCH)] = {	0x733,		0	},
455 		[C(OP_READ)] = {	0,		0x704	},
460 		[C(OP_READ)] = {	0,		0x700	},
465 		[C(OP_READ)] = {	0x431,		0x327	},
480 	.add_fields		= 0x001100005555ull,
481 	.test_adder		= 0x013300000000ull,