1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * arch/powerpc/math-emu/math_efp.c
5  * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc.
10  * Derived from arch/alpha/math-emu/math.c
11  *              arch/powerpc/math-emu/math.c
15  * fully comply with IEEE-754 floating point standard.
26 #include <asm/sfp-machine.h>
28 #include <math-emu/soft-fp.h>
29 #include <math-emu/single.h>
30 #include <math-emu/double.h>
185 	if (get_user(speinsn, (unsigned int __user *) regs->nip))  in do_spe_mathemu()
186 		return -EFAULT;  in do_spe_mathemu()
188 		return -EINVAL;         /* not an spe instruction */  in do_spe_mathemu()
200 	vc.wp[0] = current->thread.evr[fc];  in do_spe_mathemu()
201 	vc.wp[1] = regs->gpr[fc];  in do_spe_mathemu()
202 	va.wp[0] = current->thread.evr[fa];  in do_spe_mathemu()
203 	va.wp[1] = regs->gpr[fa];  in do_spe_mathemu()
204 	vb.wp[0] = current->thread.evr[fb];  in do_spe_mathemu()
205 	vb.wp[1] = regs->gpr[fb];  in do_spe_mathemu()
272 			cmp = -1;  in do_spe_mathemu()
403 			cmp = -1;  in do_spe_mathemu()
563 			cmp = -1;  in do_spe_mathemu()
655 		return -EINVAL;  in do_spe_mathemu()
659 	regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2));  in do_spe_mathemu()
660 	regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));  in do_spe_mathemu()
664 	 * If the "invalid" exception sticky bit was set by the  in do_spe_mathemu()
665 	 * processor for non-finite input, but was not set before the  in do_spe_mathemu()
669 	 * flag should be set for IEEE 754 semantics.  Other sticky  in do_spe_mathemu()
672 	 * clear sticky bits that were already set before the emulated  in do_spe_mathemu()
673 	 * instruction as they represent the user-visible sticky  in do_spe_mathemu()
676 	 * so the "inexact" sticky bit may have been set by a previous  in do_spe_mathemu()
680 	  &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;  in do_spe_mathemu()
683 	current->thread.spefscr_last = __FPU_FPSCR;  in do_spe_mathemu()
685 	current->thread.evr[fc] = vc.wp[0];  in do_spe_mathemu()
686 	regs->gpr[fc] = vc.wp[1];  in do_spe_mathemu()
688 	pr_debug("ccr = %08lx\n", regs->ccr);  in do_spe_mathemu()
695 	if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {  in do_spe_mathemu()
697 		    && (current->thread.fpexc_mode & PR_FP_EXC_DIV))  in do_spe_mathemu()
700 		    && (current->thread.fpexc_mode & PR_FP_EXC_OVF))  in do_spe_mathemu()
703 		    && (current->thread.fpexc_mode & PR_FP_EXC_UND))  in do_spe_mathemu()
706 		    && (current->thread.fpexc_mode & PR_FP_EXC_RES))  in do_spe_mathemu()
709 		    && (current->thread.fpexc_mode & PR_FP_EXC_INV))  in do_spe_mathemu()
717 		regs_add_return_ip(regs, -4);  in do_spe_mathemu()
718 		pr_debug("re-issue efp inst: %08lx\n", speinsn);  in do_spe_mathemu()
722 …printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst …  in do_spe_mathemu()
723 	return -ENOSYS;  in do_spe_mathemu()
734 	if (get_user(speinsn, (unsigned int __user *) regs->nip))  in speround_handler()
735 		return -EFAULT;  in speround_handler()
737 		return -EINVAL;         /* not an spe instruction */  in speround_handler()
741 	if (type == XCR) return -ENOSYS;  in speround_handler()
755 	s_lo = regs->gpr[fc] & SIGN_BIT_S;  in speround_handler()
756 	s_hi = current->thread.evr[fc] & SIGN_BIT_S;  in speround_handler()
757 	fgpr.wp[0] = current->thread.evr[fc];  in speround_handler()
758 	fgpr.wp[1] = regs->gpr[fc];  in speround_handler()
792 			s_lo = regs->gpr[fb] & SIGN_BIT_S;  in speround_handler()
800 			s_lo = regs->gpr[fb] & SIGN_BIT_S;  in speround_handler()
802 			s_hi = current->thread.evr[fb] & SIGN_BIT_S;  in speround_handler()
811 			s_hi = current->thread.evr[fb] & SIGN_BIT_S;  in speround_handler()
823 	 * and round toward zero with IEEE-754 complied, we just need  in speround_handler()
824 	 * to handle round toward +Inf and round toward -Inf by software.  in speround_handler()
829 		} else { /* round to -Inf */  in speround_handler()
834 					fgpr.wp[1]--; /* Z < 0, choose Z2 */  in speround_handler()
847 		} else { /* round to -Inf */  in speround_handler()
852 					fgpr.wp[1]--; /* Z < 0, choose Z2 */  in speround_handler()
863 		} else { /* round to -Inf */  in speround_handler()
868 					fgpr.wp[1]--; /* Z_low < 0, choose Z2 */  in speround_handler()
874 					fgpr.wp[0]--; /* Z_high < 0, choose Z2 */  in speround_handler()
880 		return -EINVAL;  in speround_handler()
883 	current->thread.evr[fc] = fgpr.wp[0];  in speround_handler()
884 	regs->gpr[fc] = fgpr.wp[1];  in speround_handler()
888 	if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)  in speround_handler()
889 		return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0;  in speround_handler()