Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
37 #include <asm/pci-bridge.h>
40 #include <asm/ppc-pci.h>
73 int ret, phb_id = -1; in get_phb_number()
78 * the respective device-tree properties. Firstly, try reading in get_phb_number()
79 * standard "linux,pci-domain", then try reading "ibm,opal-phbid" in get_phb_number()
80 * (only present in powernv OPAL environment), then try device-tree in get_phb_number()
89 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); in get_phb_number()
105 phb_id = (int)(prop & (MAX_PHBS - 1)); in get_phb_number()
132 phb->global_number = get_phb_number(dev); in pcibios_alloc_controller()
135 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
138 phb->dn = of_node_get(dev); in pcibios_alloc_controller()
139 phb->is_dynamic = slab_is_available(); in pcibios_alloc_controller()
159 if (phb->global_number < MAX_PHBS) in pcibios_free_controller()
160 clear_bit(phb->global_number, phb_bitmap); in pcibios_free_controller()
161 of_node_put(phb->dn); in pcibios_free_controller()
162 list_del(&phb->list_node); in pcibios_free_controller()
165 if (phb->is_dynamic) in pcibios_free_controller()
177 * The callback occurs when all references to the root bus
181 * which is associated with the 'struct pci_controller.bus'
182 * (root bus) - it expects .release_data to hold a pointer
198 bridge->release_data; in pcibios_free_controller_deferred()
200 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); in pcibios_free_controller_deferred()
212 resource_size_t pcibios_window_alignment(struct pci_bus *bus, in pcibios_window_alignment() argument
215 struct pci_controller *phb = pci_bus_to_host(bus); in pcibios_window_alignment()
217 if (phb->controller_ops.window_alignment) in pcibios_window_alignment()
218 return phb->controller_ops.window_alignment(bus, type); in pcibios_window_alignment()
228 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) in pcibios_setup_bridge() argument
230 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_setup_bridge()
232 if (hose->controller_ops.setup_bridge) in pcibios_setup_bridge()
233 hose->controller_ops.setup_bridge(bus, type); in pcibios_setup_bridge()
238 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_reset_secondary_bus()
240 if (phb->controller_ops.reset_secondary_bus) { in pcibios_reset_secondary_bus()
241 phb->controller_ops.reset_secondary_bus(dev); in pcibios_reset_secondary_bus()
286 return hose->pci_io_size; in pcibios_io_size()
288 return resource_size(&hose->io_resource); in pcibios_io_size()
301 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
302 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
320 if (address >= hose->io_base_phys && in pci_address_to_pio()
321 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
323 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
324 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
335 * Return the domain number for this bus.
337 int pci_domain_nr(struct pci_bus *bus) in pci_domain_nr() argument
339 struct pci_controller *hose = pci_bus_to_host(bus); in pci_domain_nr()
341 return hose->global_number; in pci_domain_nr()
346 * PCI bus numbers have not yet been assigned, and you need to
357 if (hose->dn == node) in pci_find_hose_for_OF_device()
359 node = node->parent; in pci_find_hose_for_OF_device()
369 if (hose->global_number == domain_nr) in pci_find_controller_for_domain()
388 list_del(&vi->list_node); in ppc_pci_intx_release()
389 irq_dispose_mapping(vi->virq); in ppc_pci_intx_release()
403 if (vi->virq == pdev->irq) { in ppc_pci_unmap_irq_line()
404 kref_put(&vi->kref, ppc_pci_intx_release); in ppc_pci_unmap_irq_line()
437 return -1; in pci_read_irq_line()
441 /* Try to get a mapping from the device-tree */ in pci_read_irq_line()
476 pci_dev->irq = virq; in pci_read_irq_line()
480 if (vitmp->virq == virq) { in pci_read_irq_line()
481 kref_get(&vitmp->kref); in pci_read_irq_line()
488 vi->virq = virq; in pci_read_irq_line()
489 kref_init(&vi->kref); in pci_read_irq_line()
490 list_add_tail(&vi->list_node, &intx_list); in pci_read_irq_line()
497 return -1; in pci_read_irq_line()
501 * Platform support for /proc/bus/pci/X/Y mmap()s.
502 * -- paulus.
506 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
510 return -EINVAL; in pci_iobar_pfn()
513 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
515 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
540 struct resource *rp = &pdev->resource[i]; in pci_phys_mem_access_prot()
541 int flags = rp->flags; in pci_phys_mem_access_prot()
546 /* In the range of this resource? */ in pci_phys_mem_access_prot()
547 if (offset < (rp->start & PAGE_MASK) || in pci_phys_mem_access_prot()
548 offset > rp->end) in pci_phys_mem_access_prot()
557 if (found->flags & IORESOURCE_PREFETCH) in pci_phys_mem_access_prot()
562 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", in pci_phys_mem_access_prot()
568 /* This provides legacy IO read access on a bus */
569 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) in pci_legacy_read() argument
572 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_read()
573 struct resource *rp = &hose->io_resource; in pci_legacy_read()
576 /* Check if port can be supported by that bus. We only check in pci_legacy_read()
577 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_read()
581 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
584 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
585 return -ENXIO; in pci_legacy_read()
586 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
587 return -ENXIO; in pci_legacy_read()
588 addr = hose->io_base_virt + port; in pci_legacy_read()
596 return -EINVAL; in pci_legacy_read()
601 return -EINVAL; in pci_legacy_read()
605 return -EINVAL; in pci_legacy_read()
608 /* This provides legacy IO write access on a bus */
609 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) in pci_legacy_write() argument
612 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_write()
613 struct resource *rp = &hose->io_resource; in pci_legacy_write()
616 /* Check if port can be supported by that bus. We only check in pci_legacy_write()
617 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_write()
621 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
624 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
625 return -ENXIO; in pci_legacy_write()
626 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
627 return -ENXIO; in pci_legacy_write()
628 addr = hose->io_base_virt + port; in pci_legacy_write()
641 return -EINVAL; in pci_legacy_write()
646 return -EINVAL; in pci_legacy_write()
650 return -EINVAL; in pci_legacy_write()
653 /* This provides legacy IO or memory mmap access on a bus */
654 int pci_mmap_legacy_page_range(struct pci_bus *bus, in pci_mmap_legacy_page_range() argument
658 struct pci_controller *hose = pci_bus_to_host(bus); in pci_mmap_legacy_page_range()
660 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
661 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
665 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
668 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
678 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
680 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", in pci_mmap_legacy_page_range()
681 current->comm, current->pid, pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
682 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
686 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
688 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_mmap_legacy_page_range()
690 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
691 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
692 return -ENXIO; in pci_mmap_legacy_page_range()
693 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
694 return -ENXIO; in pci_mmap_legacy_page_range()
695 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
697 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
699 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
700 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
701 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
702 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
703 vma->vm_page_prot); in pci_mmap_legacy_page_range()
712 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
713 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
724 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
725 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
727 *start = rsrc->start; in pci_resource_to_user()
728 *end = rsrc->end; in pci_resource_to_user()
732 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
735 * @primary: set if primary bus (32 bits only, soon to be deprecated)
744 * - We can only cope with one IO space range and up to 3 Memory space
748 * - Some busses have IO space not starting at 0, which causes trouble with
752 * - Some 32 bits platforms such as 4xx can have physical space larger than
760 struct of_pci_range range; in pci_process_bridge_OF_ranges() local
771 for_each_of_pci_range(&parser, &range) { in pci_process_bridge_OF_ranges()
772 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
777 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) in pci_process_bridge_OF_ranges()
782 switch (range.flags & IORESOURCE_TYPE_BITS) { in pci_process_bridge_OF_ranges()
785 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
786 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
787 range.pci_addr); in pci_process_bridge_OF_ranges()
789 /* We support only one IO range */ in pci_process_bridge_OF_ranges()
790 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
792 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
797 if (range.size > 0x01000000) in pci_process_bridge_OF_ranges()
798 range.size = 0x01000000; in pci_process_bridge_OF_ranges()
801 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
802 range.size); in pci_process_bridge_OF_ranges()
807 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
812 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
813 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
816 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
817 range.cpu_addr = range.pci_addr; in pci_process_bridge_OF_ranges()
821 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
822 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
823 range.pci_addr, in pci_process_bridge_OF_ranges()
824 (range.flags & IORESOURCE_PREFETCH) ? in pci_process_bridge_OF_ranges()
830 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
834 if (range.pci_addr == 0) { in pci_process_bridge_OF_ranges()
836 isa_mem_base = range.cpu_addr; in pci_process_bridge_OF_ranges()
837 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
838 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
842 hose->mem_offset[memno] = range.cpu_addr - in pci_process_bridge_OF_ranges()
843 range.pci_addr; in pci_process_bridge_OF_ranges()
844 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
848 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
849 res->flags = range.flags; in pci_process_bridge_OF_ranges()
850 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
851 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
852 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
858 int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
860 struct pci_controller *hose = pci_bus_to_host(bus); in pci_proc_domain()
865 return hose->global_number != 0; in pci_proc_domain()
882 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
892 if (dev->is_virtfn) in pcibios_fixup_resources()
898 if (!res->flags) in pcibios_fixup_resources()
901 /* If we're going to re-assign everything, we mark all resources in pcibios_fixup_resources()
902 * as unset (and 0-base them). In addition, we mark BARs starting in pcibios_fixup_resources()
904 * since in that case, we don't want to re-assign anything in pcibios_fixup_resources()
906 pcibios_resource_to_bus(dev->bus, ®, res); in pcibios_fixup_resources()
909 /* Only print message if not re-assigning */ in pcibios_fixup_resources()
913 res->end -= res->start; in pcibios_fixup_resources()
914 res->start = 0; in pcibios_fixup_resources()
915 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
931 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
933 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, in pcibios_uninitialized_bridge_resource() argument
936 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_uninitialized_bridge_resource()
937 struct pci_dev *dev = bus->self; in pcibios_uninitialized_bridge_resource()
948 if (res->flags & IORESOURCE_MEM) { in pcibios_uninitialized_bridge_resource()
949 pcibios_resource_to_bus(dev->bus, ®ion, res); in pcibios_uninitialized_bridge_resource()
951 /* If the BAR is non-0 then it's probably been initialized */ in pcibios_uninitialized_bridge_resource()
967 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && in pcibios_uninitialized_bridge_resource()
968 hose->mem_resources[i].start == hose->mem_offset[i]) in pcibios_uninitialized_bridge_resource()
977 /* If the BAR is non-0, then we consider it assigned */ in pcibios_uninitialized_bridge_resource()
978 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_uninitialized_bridge_resource()
979 if (((res->start - offset) & 0xfffffffful) != 0) in pcibios_uninitialized_bridge_resource()
983 * starting at low addresses -is- valid. What we do instead if that in pcibios_uninitialized_bridge_resource()
998 /* Fixup resources of a PCI<->PCI bridge */
999 static void pcibios_fixup_bridge(struct pci_bus *bus) in pcibios_fixup_bridge() argument
1004 struct pci_dev *dev = bus->self; in pcibios_fixup_bridge()
1006 pci_bus_for_each_resource(bus, res, i) { in pcibios_fixup_bridge()
1007 if (!res || !res->flags) in pcibios_fixup_bridge()
1009 if (i >= 3 && bus->self->transparent) in pcibios_fixup_bridge()
1017 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_bridge()
1018 res->start = 0; in pcibios_fixup_bridge()
1019 res->end = -1; in pcibios_fixup_bridge()
1023 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); in pcibios_fixup_bridge()
1026 * and clear them out so they get re-assigned later in pcibios_fixup_bridge()
1028 if (pcibios_uninitialized_bridge_resource(bus, res)) { in pcibios_fixup_bridge()
1029 res->flags = 0; in pcibios_fixup_bridge()
1035 void pcibios_setup_bus_self(struct pci_bus *bus) in pcibios_setup_bus_self() argument
1039 /* Fix up the bus resources for P2P bridges */ in pcibios_setup_bus_self()
1040 if (bus->self != NULL) in pcibios_setup_bus_self()
1041 pcibios_fixup_bridge(bus); in pcibios_setup_bus_self()
1043 /* Platform specific bus fixups. This is currently only used in pcibios_setup_bus_self()
1047 ppc_md.pcibios_fixup_bus(bus); in pcibios_setup_bus_self()
1049 /* Setup bus DMA mappings */ in pcibios_setup_bus_self()
1050 phb = pci_bus_to_host(bus); in pcibios_setup_bus_self()
1051 if (phb->controller_ops.dma_bus_setup) in pcibios_setup_bus_self()
1052 phb->controller_ops.dma_bus_setup(bus); in pcibios_setup_bus_self()
1061 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); in pcibios_bus_add_device()
1064 set_dma_ops(&dev->dev, pci_dma_ops); in pcibios_bus_add_device()
1065 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; in pcibios_bus_add_device()
1068 phb = pci_bus_to_host(dev->bus); in pcibios_bus_add_device()
1069 if (phb->controller_ops.dma_dev_setup) in pcibios_bus_add_device()
1070 phb->controller_ops.dma_dev_setup(dev); in pcibios_bus_add_device()
1090 d = dev_get_msi_domain(&dev->bus->dev); in pcibios_device_add()
1092 dev_set_msi_domain(&dev->dev, d); in pcibios_device_add()
1098 /* No special bus mastering setup handling */ in pcibios_set_master()
1101 void pcibios_fixup_bus(struct pci_bus *bus) in pcibios_fixup_bus() argument
1103 /* When called from the generic PCI probe, read PCI<->PCI bridge in pcibios_fixup_bus()
1104 * bases. This is -not- called when generating the PCI tree from in pcibios_fixup_bus()
1105 * the OF device-tree. in pcibios_fixup_bus()
1107 pci_read_bridge_bases(bus); in pcibios_fixup_bus()
1109 /* Now fixup the bus */ in pcibios_fixup_bus()
1110 pcibios_setup_bus_self(bus); in pcibios_fixup_bus()
1117 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) in skip_isa_ioresource_align()
1125 * addresses to be allocated in the 0x000-0x0ff region
1129 * the low 10 bits of the IO address. The 0x00-0xff region
1131 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1132 * but we want to try to avoid allocating at 0x2900-0x2bff
1133 * which might have be mirrored at 0x0100-0x03ff..
1139 resource_size_t start = res->start; in pcibios_align_resource()
1141 if (res->flags & IORESOURCE_IO) { in pcibios_align_resource()
1162 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
1163 if (p->end < res->start) in reparent_resources()
1165 if (res->end < p->start) in reparent_resources()
1167 if (p->start < res->start || p->end > res->end) in reparent_resources()
1168 return -1; /* not completely contained */ in reparent_resources()
1173 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
1174 res->parent = parent; in reparent_resources()
1175 res->child = *firstpp; in reparent_resources()
1176 res->sibling = *pp; in reparent_resources()
1179 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
1180 p->parent = res; in reparent_resources()
1182 p->name, p, res->name); in reparent_resources()
1190 * On the other hand, we cannot just re-allocate all devices, as it would
1196 * - I/O or memory regions not configured
1197 * - regions configured, but not enabled in the command register
1198 * - bogus I/O addresses above 64K used
1199 * - expansion ROMs left enabled (this may sound harmless, but given
1205 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1220 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
1226 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", in pcibios_allocate_bus_resources()
1227 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
1229 pci_bus_for_each_resource(bus, res, i) { in pcibios_allocate_bus_resources()
1230 if (!res || !res->flags || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
1234 if (res->flags & IORESOURCE_UNSET) in pcibios_allocate_bus_resources()
1237 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
1238 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
1241 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
1245 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
1251 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", in pcibios_allocate_bus_resources()
1252 bus->self ? pci_name(bus->self) : "PHB", bus->number, in pcibios_allocate_bus_resources()
1253 i, res, pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
1255 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
1256 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
1274 i, bus->number); in pcibios_allocate_bus_resources()
1282 res->start = 0; in pcibios_allocate_bus_resources()
1283 res->end = -1; in pcibios_allocate_bus_resources()
1284 res->flags = 0; in pcibios_allocate_bus_resources()
1287 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
1293 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
1299 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
1306 r->flags |= IORESOURCE_UNSET; in alloc_resource()
1307 r->end -= r->start; in alloc_resource()
1308 r->start = 0; in alloc_resource()
1322 r = &dev->resource[idx]; in pcibios_allocate_resources()
1323 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
1325 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
1332 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
1341 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
1342 if (r->flags) { in pcibios_allocate_resources()
1347 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
1351 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
1352 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
1359 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) in pcibios_reserve_legacy_regions() argument
1361 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_reserve_legacy_regions()
1366 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); in pcibios_reserve_legacy_regions()
1369 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
1371 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
1374 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
1375 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
1376 res->start = offset; in pcibios_reserve_legacy_regions()
1377 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
1379 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
1382 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1389 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
1390 offset = hose->mem_offset[i]; in pcibios_reserve_legacy_regions()
1391 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
1394 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
1395 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
1402 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
1403 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
1404 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
1405 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
1410 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1429 * bus available resources to avoid allocating things on top of them in pcibios_resource_survey()
1447 * rest of the code later, for now, keep it as-is as our main
1448 * resource allocation function doesn't deal with sub-trees yet.
1450 void pcibios_claim_one_bus(struct pci_bus *bus) in pcibios_claim_one_bus() argument
1455 list_for_each_entry(dev, &bus->devices, bus_list) { in pcibios_claim_one_bus()
1460 if (r->parent || !r->start || !r->flags) in pcibios_claim_one_bus()
1473 list_for_each_entry(child_bus, &bus->children, node) in pcibios_claim_one_bus()
1482 * added to a bus, this include calling it for a PHB that is just
1485 void pcibios_finish_adding_to_bus(struct pci_bus *bus) in pcibios_finish_adding_to_bus() argument
1487 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", in pcibios_finish_adding_to_bus()
1488 pci_domain_nr(bus), bus->number); in pcibios_finish_adding_to_bus()
1490 /* Allocate bus and devices resources */ in pcibios_finish_adding_to_bus()
1491 pcibios_allocate_bus_resources(bus); in pcibios_finish_adding_to_bus()
1492 pcibios_claim_one_bus(bus); in pcibios_finish_adding_to_bus()
1494 if (bus->self) in pcibios_finish_adding_to_bus()
1495 pci_assign_unassigned_bridge_resources(bus->self); in pcibios_finish_adding_to_bus()
1497 pci_assign_unassigned_bus_resources(bus); in pcibios_finish_adding_to_bus()
1501 pci_bus_add_devices(bus); in pcibios_finish_adding_to_bus()
1507 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_enable_device()
1509 if (phb->controller_ops.enable_device_hook) in pcibios_enable_device()
1510 if (!phb->controller_ops.enable_device_hook(dev)) in pcibios_enable_device()
1511 return -EINVAL; in pcibios_enable_device()
1518 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_disable_device()
1520 if (phb->controller_ops.disable_device) in pcibios_disable_device()
1521 phb->controller_ops.disable_device(dev); in pcibios_disable_device()
1526 return (unsigned long) hose->io_base_virt - _IO_BASE; in pcibios_io_space_offset()
1537 res = &hose->io_resource; in pcibios_setup_phb_resources()
1539 if (!res->flags) { in pcibios_setup_phb_resources()
1542 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
1553 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
1554 if (!res->flags) in pcibios_setup_phb_resources()
1557 offset = hose->mem_offset[i]; in pcibios_setup_phb_resources()
1577 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_read_config() argument
1584 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_write_config() argument
1603 static struct pci_bus bus; in fake_pci_bus() local
1606 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); in fake_pci_bus()
1608 bus.number = busnr; in fake_pci_bus()
1609 bus.sysdata = hose; in fake_pci_bus()
1610 bus.ops = hose? hose->ops: &null_pci_ops; in fake_pci_bus()
1611 return &bus; in fake_pci_bus()
1615 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1618 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1629 int early_find_capability(struct pci_controller *hose, int bus, int devfn, in EARLY_PCI_OP()
1632 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); in EARLY_PCI_OP()
1635 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) in pcibios_get_phb_of_node() argument
1637 struct pci_controller *hose = bus->sysdata; in pcibios_get_phb_of_node()
1639 return of_node_get(hose->dn); in pcibios_get_phb_of_node()
1643 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1649 struct pci_bus *bus; in pcibios_scan_phb() local
1650 struct device_node *node = hose->dn; in pcibios_scan_phb()
1658 /* Wire up PHB bus resources */ in pcibios_scan_phb()
1661 hose->busn.start = hose->first_busno; in pcibios_scan_phb()
1662 hose->busn.end = hose->last_busno; in pcibios_scan_phb()
1663 hose->busn.flags = IORESOURCE_BUS; in pcibios_scan_phb()
1664 pci_add_resource(&resources, &hose->busn); in pcibios_scan_phb()
1666 /* Create an empty bus for the toplevel */ in pcibios_scan_phb()
1667 bus = pci_create_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
1668 hose->ops, hose, &resources); in pcibios_scan_phb()
1669 if (bus == NULL) { in pcibios_scan_phb()
1670 pr_err("Failed to create bus for PCI domain %04x\n", in pcibios_scan_phb()
1671 hose->global_number); in pcibios_scan_phb()
1675 hose->bus = bus; in pcibios_scan_phb()
1679 if (node && hose->controller_ops.probe_mode) in pcibios_scan_phb()
1680 mode = hose->controller_ops.probe_mode(bus); in pcibios_scan_phb()
1683 of_scan_bus(node, bus); in pcibios_scan_phb()
1686 pci_bus_update_busn_res_end(bus, 255); in pcibios_scan_phb()
1687 hose->last_busno = pci_scan_child_bus(bus); in pcibios_scan_phb()
1688 pci_bus_update_busn_res_end(bus, hose->last_busno); in pcibios_scan_phb()
1698 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { in pcibios_scan_phb()
1700 list_for_each_entry(child, &bus->children, node) in pcibios_scan_phb()
1708 int class = dev->class >> 8; in fixup_hide_host_resource_fsl()
1710 int prog_if = dev->class & 0xf; in fixup_hide_host_resource_fsl()
1715 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && in fixup_hide_host_resource_fsl()
1717 (dev->bus->parent == NULL)) { in fixup_hide_host_resource_fsl()
1719 r->start = 0; in fixup_hide_host_resource_fsl()
1720 r->end = 0; in fixup_hide_host_resource_fsl()
1721 r->flags = 0; in fixup_hide_host_resource_fsl()