powerpc/kernel/head_book3s_32.S

41 	li	RA,0;			\
44 	lwz	RA,(n*16)+0(reg);	\
73  * 0, running with virtual == physical mapping.
78  * from 0x380000 - 0x400000, which is mapped in already.
82  *  r3: 'BooX' (0x426f6f58)
84  *  r5: 0
91  *   r4: initrd_start or if no initrd then 0
92  *   r5: initrd_end - unused if r4 is 0
108 	cmpwi	0,r5,0
114 0:	mflr	r8			/* r8 = runtime addr here */
115 	addis	r8,r8,(_stext - 0b)@ha
116 	addi	r8,r8,(_stext - 0b)@l	/* current runtime base addr */
129 1:	lis	r31,0x426f
130 	ori	r31,r31,0x6f58
131 	cmpw	0,r3,r31
138 	li	r24,0			/* cpu # */
170  * Call setup_cpu for CPU 0 and initialize 6xx Idle
173 	li	r24,0			/* cpu# */
180  * We need to run with _start at physical address 0.
181  * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
182  * the exception vectors at 0 (and therefore this copy
190 	cmplw	0,r4,r5			/* already running at PHYSICAL_START? */
213 	. = 0xc0			/* for prep bootloader */
218 	stw	r3,__secondary_hold_acknowledge@l(0)
220 100:	lwz	r4,0(0)
222 	cmpw	0,r4,r3
224 	/* our cpu # was at addr 0 - go */
233 	.long	0
263 	cmpwi	cr1, r1, 0
268 7:	EXCEPTION_PROLOG_2 0x200 MachineCheck
271 	twi	31, 0, 0
360 	START_EXCEPTION(0x800, FPUnavailable)
383 	EXCEPTION(0xa00, Trap_0a, unknown_exception)
384 	EXCEPTION(0xb00, Trap_0b, unknown_exception)
391 	EXCEPTION(0xe00, Trap_0e, unknown_exception)
394  * The Altivec unavailable trap is at 0x0f20.  Foo.
395  * We effectively remap it to 0x3000.
424 	cmplw	0,r1,r3
428 	rlwinm	r2, r2, 28, 0xfffff000
436 	lwz	r2,0(r2)		/* get pmd entry */
437 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
440 	lwz	r0,0(r2)		/* get linux-style pte */
445 	ori	r1, r1, 0xe06		/* clear out reserved bits */
446 	andc	r1, r0, r1		/* PP = user? 1 : 0 */
448 	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */
453 	mtcrf	0x80,r3
459 	addis	r1,r1,0x2000
461 	andi.	r2,r3,0xFFFF	/* Clear upper bits of SRR1 */
465 	rlwinm.	r2,r2,0,31,31	/* Check for little endian access */
471 	mtcrf	0x80,r3		/* Restore CR0 */
489 	cmplw	0,r1,r3
492 	rlwinm	r2, r2, 28, 0xfffff000
498 	lwz	r2,0(r2)		/* get pmd entry */
499 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
502 	lwz	r0,0(r2)		/* get linux-style pte */
511 	ori	r1,r1,0xe04		/* clear out reserved bits */
512 	andc	r1,r0,r1		/* PP = user? rw? 1: 3: 0 */
514 	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */
528 	mtcrf	0x80,r2
533 	mtcrf	0x80,r2
540 	addis	r1,r1,0x2000
542 	andi.	r2,r3,0xFFFF	/* Clear upper bits of SRR1 */
545 	rlwinm.	r2,r2,0,31,31	/* Check for little endian access */
551 	mtcrf	0x80,r3		/* Restore CR0 */
569 	cmplw	0,r1,r3
572 	rlwinm	r2, r2, 28, 0xfffff000
578 	lwz	r2,0(r2)		/* get pmd entry */
579 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
582 	lwz	r0,0(r2)		/* get linux-style pte */
587 	li	r1,0xe06		/* clear out reserved bits & PP msb */
588 	andc	r1,r0,r1		/* PP = user? 1: 0 */
590 	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */
594 	mtcrf	0x80,r2
606 	mtcrf	0x80,r2
611 	mtcrf	0x80,r2
624 	EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception)
625 	EXCEPTION(0x1400, SMI, SMIException)
626 	EXCEPTION(0x1500, Trap_15, unknown_exception)
627 	EXCEPTION(0x1600, Trap_16, altivec_assist_exception)
628 	EXCEPTION(0x1700, Trap_17, TAUException)
629 	EXCEPTION(0x1800, Trap_18, unknown_exception)
630 	EXCEPTION(0x1900, Trap_19, unknown_exception)
631 	EXCEPTION(0x1a00, Trap_1a, unknown_exception)
632 	EXCEPTION(0x1b00, Trap_1b, unknown_exception)
633 	EXCEPTION(0x1c00, Trap_1c, unknown_exception)
634 	EXCEPTION(0x1d00, Trap_1d, unknown_exception)
635 	EXCEPTION(0x1e00, Trap_1e, unknown_exception)
636 	EXCEPTION(0x1f00, Trap_1f, unknown_exception)
637 	EXCEPTION(0x2000, RunMode, RunModeException)
638 	EXCEPTION(0x2100, Trap_21, unknown_exception)
639 	EXCEPTION(0x2200, Trap_22, unknown_exception)
640 	EXCEPTION(0x2300, Trap_23, unknown_exception)
641 	EXCEPTION(0x2400, Trap_24, unknown_exception)
642 	EXCEPTION(0x2500, Trap_25, unknown_exception)
643 	EXCEPTION(0x2600, Trap_26, unknown_exception)
644 	EXCEPTION(0x2700, Trap_27, unknown_exception)
645 	EXCEPTION(0x2800, Trap_28, unknown_exception)
646 	EXCEPTION(0x2900, Trap_29, unknown_exception)
647 	EXCEPTION(0x2a00, Trap_2a, unknown_exception)
648 	EXCEPTION(0x2b00, Trap_2b, unknown_exception)
649 	EXCEPTION(0x2c00, Trap_2c, unknown_exception)
650 	EXCEPTION(0x2d00, Trap_2d, unknown_exception)
651 	EXCEPTION(0x2e00, Trap_2e, unknown_exception)
652 	EXCEPTION(0x2f00, Trap_2f, unknown_exception)
655 	. = 0x3000
702 	li	r3, 0
737 	EXCEPTION_PROLOG 0xf20 AltiVecUnavailable
749 	EXCEPTION_PROLOG 0xf00 PerformanceMonitor
762 	li	r6,0			/* Destination offset */
763 	li	r5,0x4000		/* # bytes of memory to copy */
764 	bl	copy_and_flush		/* copy the first 0x4000 bytes */
774  * Copy routine used to copy the kernel to start at physical address 0
791 	cmplw	0,r6,r5
803 	stw	r3, __secondary_hold_acknowledge@l(0)
809 	/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
810 	li	r24,0
818 	/* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
819 	   set to map the 0xf0000000 - 0xffffffff region */
821 	rlwinm	r0,r0,0,28,26		/* clear DR (0x10) */
827 	/* Copy some CPU settings from CPU 0 */
845 	li	r0,0
847 	stw	r0,0(r3)
860 	rlwinm	r4, r4, 4, 0xffff01ff
879  * IR=0 and DR=0.
912 	LOAD_BAT(0,r3,r4,r5)
927 	mtctr	r0		/* for context 0 */
929 	lis	r3, SR_NX@h	/* Kp = 0, Ks = 0, VSID = 0 */
931 	li	r3, 0		/* Kp = 0, Ks = 0, VSID = 0 */
933 	li	r4, 0
935 	addi	r3, r3, 0x111	/* increment VSID */
936 	addis	r4, r4, 0x1000	/* address of next segment */
939 	mtctr	r0			/* for context 0 */
940 	rlwinm	r3, r3, 0, ~SR_NX	/* Nx = 0 */
941 	rlwinm	r3, r3, 0, ~SR_KS	/* Ks = 0 */
944 	addi	r3, r3, 0x111	/* increment VSID */
945 	addis	r4, r4, 0x1000	/* address of next segment */
964 	rlwinm	r4, r4, 4, 0xffff01ff
971 	li	r0,0
980 	li	r3,0
1011 	stw	r5, 0xf0(0)	/* This much match your Abatron config */
1015 	stw	r6, 0(r5)
1035 	li	r10,0
1087 	rlwinm	r0, r6, 0, ~MSR_RI
1088 	rlwinm	r0, r0, 0, ~MSR_EE
1099 	LOAD_BAT(0, r3, r4, r5)
1116 	lis	r10, 0x40
1117 1:	addic.	r10, r10, -0x1000
1143 	ori	r8,r8,0x12		/* R/W access, M=1 */
1147 	ori	r11,r11,BL_256M<<2|0x2	/* set up BAT registers for 604 */
1167 	cmpwi	cr0,r8,0
1169 	lwz	r11,0(r8)
1179 	lis	r8, 0xf000
1180 	ori	r8, r8,	0x002a
1183 	lis	r11, 0xf000
1195 	lis	r8, 0x0c00
1197 	lis	r8, 0x0d00
1205 	lis	r11, 0xfffe	/* top 128K */
1206 	ori	r8, r8, 0x002a	/* uncached, guarded ,rw */
1207 	ori	r11, r11, 0x2	/* 128K, Vs=1, Vp=0 */