include/asm/reg.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N	0			/*  Non-transactional */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK		0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS	0xf000000000000000 /* Power-saving Level Status */
171 #define PSSCR_GUEST_VIS	0xf0000000000003ffUL /* Guest-visible PSSCR fields */
172 #define PSSCR_FAKE_SUSPEND	0x00000400 /* Fake-suspend bit (P9 DD2.2) */
173 #define PSSCR_FAKE_SUSPEND_LG	10	   /* Fake-suspend bit position */
181 #define FPSCR_ZX	0x04000000	/* Zero-divide exception summary */
184 #define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
201 #define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
208 #define SPEFSCR_FXH	0x10000000	/* Embedded FP sticky bit high */
213 #define SPEFSCR_FINXS	0x00200000	/* Embedded FP inexact sticky */
214 #define SPEFSCR_FINVS	0x00100000	/* Embedded FP invalid op. sticky */
215 #define SPEFSCR_FDBZS	0x00080000	/* Embedded FP div by zero sticky */
216 #define SPEFSCR_FUNFS	0x00040000	/* Embedded FP underflow sticky */
217 #define SPEFSCR_FOVFS	0x00020000	/* Embedded FP overflow sticky */
222 #define SPEFSCR_FX	0x00001000	/* Embedded FP sticky bit */
256 #define TEXASR_FC_LG	(63 - 7)	/* Failure Code */
257 #define TEXASR_AB_LG	(63 - 31)	/* Abort */
258 #define TEXASR_SU_LG	(63 - 32)	/* Suspend */
259 #define TEXASR_HV_LG	(63 - 34)	/* Hypervisor state*/
260 #define TEXASR_PR_LG	(63 - 35)	/* Privilege level */
261 #define TEXASR_FS_LG	(63 - 36)	/* failure summary */
262 #define TEXASR_EX_LG	(63 - 37)	/* TFIAR exact bit */
263 #define TEXASR_ROT_LG	(63 - 38)	/* ROT bit */
334  * indicates an attempt at executing from a no-execute PTE
385 #define SPRN_HDEXCR_RO	0x1C7	/* Hypervisor DEXCR (non-privileged, readonly) */
386 #define SPRN_HASHKEYR	0x1D4	/* Non-privileged hashst/hashchk key register */
388 #define SPRN_DEXCR_RO	0x32C	/* DEXCR (non-privileged, readonly) */
394 #define   DEXCR_PR_NPHIE  0x04000000UL /* 5: Non-Privileged Hash Instruction Enable */
406 #define SPRN_RWMR	0x375	/* Region-Weighting Mode Register */
459 #define   LPCR_ONL		ASM_CONST(0x0000000000040000)	/* online - PURR/SPURR count */
486 #define   HMER_DEBUG_TRIG	(1ul << (63 - 17)) /* Debug trigger */
489 #define   PCR_VEC_DIS	(__MASK(63-0))	/* Vec. disable (bit NA since POWER8) */
490 #define   PCR_VSX_DIS	(__MASK(63-1))	/* VSX disable (bit NA since POWER8) */
491 #define   PCR_TM_DIS	(__MASK(63-2))	/* Trans. memory disable (POWER8) */
492 #define   PCR_MMA_DIS	(__MASK(63-3)) /* Matrix-Multiply Accelerator */
559 #define HID0_HDICE_SH	(63 - 23)	/* 970 HDEC interrupt enable */
565 #define HID0_TBEN	(1<<26)		/* Timebase enable - 745x */
568 #define HID0_STEN	(1<<24)		/* Software table search enable - 745x */
569 #define HID0_HIGH_BAT	(1<<23)		/* Enable high BATs - 7455 */
574 #define HID0_BHTCLR	(1<<18)		/* Clear branch history table - 7450 */
575 #define HID0_XAEN	(1<<17)		/* Extended addressing enable - 7450 */
576 #define HID0_NHR	(1<<16)		/* Not hard reset (software bit-7450)*/
588 #define HID0_LRSTK	(1<<4)		/* Link register stack - 745x */
591 #define HID0_FOLD	(1<<3)		/* Branch Folding enable - 745x */
594 #define HID0_NOPDST	(1<<1)		/* No-op dst, dstt, etc. instr. */
595 #define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */
604 #define HID0_POWER9_RADIX	__MASK(63 - 8)
627 #define  HID4_LPES0	 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
628 #define	 HID4_RMLS2_SH	 (63 - 2)	/* Real mode limit bottom 2 bits */
629 #define	 HID4_LPID5_SH	 (63 - 6)	/* partition ID bottom 4 bits */
630 #define	 HID4_RMOR_SH	 (63 - 22)	/* real mode offset (16 bits) */
632 #define  HID4_LPES1	 (1 << (63-57))	/* LPAR env. sel. bit 1 */
633 #define  HID4_RMLS0_SH	 (63 - 58)	/* Real mode limit top bit */
699 #define L2CR_L2WT		0x00080000	/* L2 write-through */
723 #define L3CR_L3PSP		0x0000e000	/* L3 P-clock sample point */
728 #define L3CR_L3NIRCA		0x00000080	/* L3 non-integer ratio clock adj. */
772  * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
774  * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
781 #define   SRR1_ISI_N_G_OR_CIP	0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instru…
808 #define   SRR1_BOUNDARY		0x10000000 /* Prefixed instruction crosses 64-byte boundary */
876 #define   MMCR0_PMCC_U6	0x00080000UL /* PMC1-6 are R/W by user (PR) */
901 #define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */
921 #define SPRN_WORT	895	/* Workload optimization register - thread */
922 #define SPRN_WORC	863	/* Workload optimization register - core */
1044 #else /* 32-bit */
1088  * All 64-bit:
1089  *	- SPRG1 stores PACA pointer except 64-bit server in
1092  * 64-bit server:
1093  *	- SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1094  *	- SPRG2 scratch for exception vectors
1095  *	- SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1096  *      - HSPRG0 stores PACA in HV mode
1097  *      - HSPRG1 scratch for "HV" exceptions
1099  * 64-bit embedded
1100  *	- SPRG0 generic exception scratch
1101  *	- SPRG2 TLB exception stack
1102  *	- SPRG3 critical exception scratch (user visible, sorry!)
1103  *	- SPRG4 unused (user visible)
1104  *	- SPRG6 TLB miss scratch (user visible, sorry !)
1105  *	- SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1106  *	- SPRG8 machine check exception scratch
1107  *	- SPRG9 debug exception scratch
1109  * All 32-bit:
1110  *	- SPRG3 current thread_struct physical addr pointer
1113  * 32-bit classic:
1114  *	- SPRG0 scratch for exception vectors
1115  *	- SPRG1 scratch for exception vectors
1116  *	- SPRG2 indicator that we are in RTAS
1117  *	- SPRG4 (603 only) pseudo TLB LRU data
1119  * 32-bit 40x:
1120  *	- SPRG0 scratch for exception vectors
1121  *	- SPRG1 scratch for exception vectors
1122  *	- SPRG2 scratch for exception vectors
1123  *	- SPRG4 scratch for exception vectors (not 403)
1124  *	- SPRG5 scratch for exception vectors (not 403)
1125  *	- SPRG6 scratch for exception vectors (not 403)
1126  *	- SPRG7 scratch for exception vectors (not 403)
1128  * 32-bit 440 and FSL BookE:
1129  *	- SPRG0 scratch for exception vectors
1130  *	- SPRG1 scratch for exception vectors (*)
1131  *	- SPRG2 scratch for crit interrupts handler
1132  *	- SPRG4 scratch for exception vectors
1133  *	- SPRG5 scratch for exception vectors
1134  *	- SPRG6 scratch for machine check handler
1135  *	- SPRG7 scratch for exception vectors
1136  *	- SPRG9 scratch for debug vectors (e500 only)
1143  * 32-bit 8xx:
1144  *	- SPRG0 scratch for exception vectors
1145  *	- SPRG1 scratch for exception vectors
1146  *	- SPRG2 scratch for exception vectors
1277  * IBM has further subdivided the standard PowerPC 16-bit version and
1345 /* 64-bit processors */