include/asm/cpm2.h

1 /* SPDX-License-Identifier: GPL-2.0 */
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
79 /* The number of pages of host memory we allocate for CPM.  This is
157  * get some microcode patches :-).
158  * The parameter ram space for the SMCs is fifty-some bytes, and
357 	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
358 	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
369 	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
370 	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
515 /* Generic FCC parameter ram.
545 	uint	fen_camptr;	/* CAM address */
555 	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
556 	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
597 	uint	fen_cambuf;	/* Internal CAM buffer pointer */
625 #define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
627 #define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
657 	ushort ss_max;		/* steady-state maximum transfer size */
670 	u_char res1[20];	/* pad to 64-byte length */
675 #define IDMA_DCM_FB		((ushort)0x8000) /* fly-by mode */
679 #define IDMA_DCM_DMA_WRAP_64	((ushort)0x0000) /* 64-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_128	((ushort)0x0040) /* 128-byte DMA xfer buffer */
681 #define IDMA_DCM_DMA_WRAP_256	((ushort)0x0080) /* 256-byte DMA xfer buffer */
682 #define IDMA_DCM_DMA_WRAP_512	((ushort)0x00c0) /* 512-byte DMA xfer buffer */
683 #define IDMA_DCM_DMA_WRAP_1024	((ushort)0x0100) /* 1024-byte DMA xfer buffer */
684 #define IDMA_DCM_DMA_WRAP_2048	((ushort)0x0140) /* 2048-byte DMA xfer buffer */
690 #define IDMA_DCM_SD_MEM2MEM	((ushort)0x0000) /* memory-to-memory xfer */
691 #define IDMA_DCM_SD_PER2MEM	((ushort)0x0002) /* peripheral-to-memory xfer */
692 #define IDMA_DCM_SD_MEM2PER	((ushort)0x0001) /* memory-to-peripheral xfer */
713 #define IDMA_BD_DBO_LE	((uint)0x00040000)	/* little-end dest byte order */
714 #define IDMA_BD_DBO_BE	((uint)0x00080000)	/* big-end dest byte order */
717 #define IDMA_BD_SBO_LE	((uint)0x00000800)	/* little-end src byte order */
718 #define IDMA_BD_SBO_BE	((uint)0x00001000)	/* big-end src byte order */
721 /* per-channel IDMA registers
778 /*-----------------------------------------------------------------------
779  * CMXFCR - CMX FCC Clock Route Register
845 /*-----------------------------------------------------------------------
846  * CMXSCR - CMX SCC Clock Route Register
937 /*-----------------------------------------------------------------------
938  * SIUMCR - SIU Module Configuration Register				 4-31
945 #define SIUMCR_DPPC01	0x04000000	/* - " -			*/
946 #define SIUMCR_DPPC10	0x08000000	/* - " -			*/
947 #define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
949 #define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
950 #define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
951 #define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
953 #define SIUMCR_LBPC01	0x00400000	/* - " -			*/
954 #define SIUMCR_LBPC10	0x00800000	/* - " -			*/
955 #define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
957 #define SIUMCR_APPC01	0x00100000	/* - " -			*/
958 #define SIUMCR_APPC10	0x00200000	/* - " -			*/
959 #define SIUMCR_APPC11	0x00300000	/* - " -			*/
961 #define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
962 #define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
963 #define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
965 #define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
966 #define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
967 #define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
969 #define SIUMCR_MMR01	0x00004000	/* - " -			*/
970 #define SIUMCR_MMR10	0x00008000	/* - " -			*/
971 #define SIUMCR_MMR11	0x0000c000	/* - " -			*/
974 /*-----------------------------------------------------------------------
975  * SCCR - System Clock Control Register					 9-8
977 #define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
979 #define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
989  * in order to use clock-computing stuff below for the FCC x
993 #define PC_CLK(x)	((uint)(1<<(x-1)))	/* FCC CLK I/O ports */
995 #define CMXFCR_RF1CS(x)	((uint)((x-5)<<27))	/* FCC1 Receive Clock Source */
996 #define CMXFCR_TF1CS(x)	((uint)((x-5)<<24))	/* FCC1 Transmit Clock Source */
997 #define CMXFCR_RF2CS(x)	((uint)((x-9)<<19))	/* FCC2 Receive Clock Source */
998 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16))	/* FCC2 Transmit Clock Source */
999 #define CMXFCR_RF3CS(x)	((uint)((x-9)<<11))	/* FCC3 Receive Clock Source */
1000 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))	/* FCC3 Transmit Clock Source */