Lines Matching +full:6 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
222 vmulouw 11, 6, 2
227 vaddudm 14, 14, 11
229 vmulouw 11, 6, 3
233 vaddudm 15, 15, 11
240 vmulouw 11, 6, 26
242 vaddudm 16, 16, 11
249 vmulouw 11, 6, 27
251 vaddudm 17, 17, 11
258 vmulouw 11, 6, 28
260 vaddudm 18, 18, 11
270 vmuleuw 11, 6, 2
275 vaddudm 14, 14, 11
281 vmuleuw 11, 6, 3
286 vaddudm 15, 15, 11
292 vmuleuw 11, 6, 26
297 vaddudm 16, 16, 11
303 vmuleuw 11, 6, 27
308 vaddudm 17, 17, 11
314 vmuleuw 11, 6, 28
319 vaddudm 18, 18, 11
360 vmr 6, 28
377 vsld 11, 29, 13
381 vaddudm 2, 11, 29
387 vmrgow 28, 28, 6
393 vsld 11, 29, 13
397 vaddudm 2, 11, 29
407 xxlor 6, 33, 33
429 vsld 11, 29, 13
433 vaddudm 2, 11, 29
444 vsrd 11, 17, 31
447 vaddudm 18, 18, 11
451 vsrd 11, 15, 31
456 vaddudm 6, 16, 11
458 vsrd 13, 6, 31
459 vand 6, 6, 25
464 vsrd 11, 7, 31
468 vaddudm 8, 8, 11
479 ld 11, 0(10)
486 lvx 25, 0, 10 # v25 - mask
496 and. 9, 9, 11
568 vperm 14, 11, 12, 17
569 vperm 15, 11, 12, 18
572 vsrd 11, 10, 31 # 12 bits left
577 vor 11, 11, 12
578 vand 11, 11, 25 # a2
586 vaddudm 22, 6, 11
595 vperm 14, 11, 12, 17
596 vperm 15, 11, 12, 18
599 vsrd 11, 10, 31 # 12 bits left
605 vor 11, 11, 12
606 vand 11, 11, 25 # a2
614 vmrgow 6, 11, 22
619 addi 5, 5, -64 # len -= 64
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
646 vsrd 11, 17, 31
649 vaddudm 18, 18, 11
653 vsrd 11, 15, 31
658 vaddudm 6, 16, 11
660 vsrd 13, 6, 31
661 vand 6, 6, 25
666 vsrd 11, 7, 31
670 vaddudm 8, 8, 11
679 vperm 14, 11, 12, 17
680 vperm 15, 11, 12, 18
685 vperm 17, 11, 12, 17
686 vperm 18, 11, 12, 18
693 vsrd 11, 10, 31 # 12 bits left
705 vor 11, 11, 12
706 vand 11, 11, 25 # a2
717 vaddudm 6, 6, 22
724 vmrgow 6, 11, 6
729 addi 5, 5, -64 # len -= 64
741 xxlor 33, 6, 6
757 vaddudm 6, 16, 11
769 vsrd 11, 7, 31
772 vaddudm 8, 8, 11
776 vsrd 11, 5, 31
781 vaddudm 6, 6, 11
783 vsrd 13, 6, 31
784 vand 6, 6, 25
789 vsrd 11, 7, 31
795 vaddudm 6, 6, 10
796 vaddudm 8, 8, 11
805 vspltisb 11, 12
806 vsrd 12, 6, 11
807 vsld 6, 6, 31
808 vsld 6, 6, 31
809 vor 20, 20, 6
810 vspltisb 11, 14
811 vsld 7, 7, 11
814 vsld 8, 8, 11
846 ld 11, 0(10)
853 and. 9, 9, 11 # cramp mask r0
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
878 vmsumudm 7, 6, 0, 9 # h0 * r0, h1 * s1
881 vmsumudm 11, 6, 1, 9 # h0 * r1, h1 * r0
882 vmsumudm 10, 8, 2, 11 # d1 += h2 * s1
885 vmsumudm 11, 8, 3, 9 # d2 = h2 * r0
899 mfvsrld 29, 32+11
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
957 add 11, 25, 4
970 mr 24, 6 # highbit
975 ld 20, 0(11)
976 ld 21, 8(11)
977 addi 11, 11, 16
984 mtvsrdd 32+6, 27, 28 # h0, h1
1035 ld 11, 8(3)
1039 # h + 5 + (-p)
1040 mr 6, 10
1041 mr 7, 11
1043 addic. 6, 6, 5
1049 mr 10, 6
1050 mr 11, 7
1054 ld 6, 0(4)
1056 addc 10, 10, 6
1057 adde 11, 11, 7
1061 std 11, 8(5)