boot/dts/yosemite.dts

19 	dcr-parent = <&{/cpus/cpu@0}>;
32 		#size-cells = <0>;
34 		cpu@0 {
37 			reg = <0x00000000>;
38 			clock-frequency = <0>; /* Filled in by zImage */
39 			timebase-frequency = <0>; /* Filled in by zImage */
51 		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
57 		cell-index = <0>;
58 		dcr-reg = <0x0c0 0x009>;
59 		#address-cells = <0>;
60 		#size-cells = <0>;
68 		dcr-reg = <0x0d0 0x009>;
69 		#address-cells = <0>;
70 		#size-cells = <0>;
72 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
78 		dcr-reg = <0x00e 0x002>;
83 		dcr-reg = <0x00c 0x002>;
91 		clock-frequency = <0>; /* Filled in by zImage */
95 			dcr-reg = <0x010 0x002>;
100 			dcr-reg = <0x100 0x027>;
105 			dcr-reg = <0x180 0x062>;
109 			interrupts = <0x0 0x1 0x2 0x3 0x4>;
111 			#address-cells = <0>;
112 			#size-cells = <0>;
113 			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
114 					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
115 					/*SERR*/  0x2 &UIC1 0x0 0x4
116 					/*TXDE*/  0x3 &UIC1 0x1 0x4
117 					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
127 			ranges = <0x00000000 0x00000000 0x00000000 0x80000000
128 			          0x80000000 0x00000000 0x80000000 0x80000000>;
130 			interrupts = <0x7 0x4>;
131 			clock-frequency = <0>; /* Filled in by zImage */
135 				dcr-reg = <0x012 0x002>;
138 				clock-frequency = <0>; /* Filled in by zImage */
139 				interrupts = <0x5 0x1>;
142 				nor_flash@0,0 {
145 					reg = <0x00000000 0x00000000 0x04000000>;
148 					partition@0 {
150 						reg = <0x00000000 0x001e0000>;
154 						reg = <0x001e0000 0x00020000>;
158 						reg = <0x00200000 0x01400000>;
162 						reg = <0x01600000 0x00400000>;
166 						reg = <0x01a00000 0x02540000>;
170 						reg = <0x03f40000 0x00040000>;
174 						reg = <0x03f80000 0x00080000>;
182 				reg = <0xef600300 0x00000008>;
183 				virtual-reg = <0xef600300>;
184 				clock-frequency = <0>; /* Filled in by zImage */
187 				interrupts = <0x0 0x4>;
193 				reg = <0xef600400 0x00000008>;
194 				virtual-reg = <0xef600400>;
195 				clock-frequency = <0>;
196 				current-speed = <0>;
198 				interrupts = <0x1 0x4>;
204 				reg = <0xef600500 0x00000008>;
205 				virtual-reg = <0xef600500>;
206 				clock-frequency = <0>;
207 				current-speed = <0>;
209 				interrupts = <0x3 0x4>;
216 				reg = <0xef600600 0x00000008>;
217 				virtual-reg = <0xef600600>;
218 				clock-frequency = <0>;
219 				current-speed = <0>;
221 				interrupts = <0x4 0x4>;
227 				reg = <0xef600700 0x00000014>;
229 				interrupts = <0x2 0x4>;
234 				reg = <0xef600800 0x00000014>;
236 				interrupts = <0x7 0x4>;
241 				reg = <0xef600900 0x00000006>;
242 				interrupts = <0x8 0x4>;
248 				reg = <0xef600d00 0x0000000c>;
255 				interrupts = <0x1c 0x4 0x1d 0x4>;
256 				reg = <0xef600e00 0x00000070>;
259 				mal-tx-channel = <0 1>;
260 				mal-rx-channel = <0>;
261 				cell-index = <0>;
266 				phy-map = <0x00000000>;
268 				zmii-channel = <0>;
275 				interrupts = <0x1e 0x4 0x1f 0x4>;
276 				reg = <0xef600f00 0x00000070>;
286 				phy-map = <0x00000000>;
293 				reg = <0xef601000 0x00000080>;
294 				interrupts = <0x8 0x4 0x9 0x4>;
306 			reg = <0x00000000 0xeec00000 0x00000008	/* Config space access */
307 			       0x00000000 0xeed00000 0x00000004	/* IACK */
308 			       0x00000000 0xeed00000 0x00000004	/* Special cycle */
309 			       0x00000000 0xef400000 0x00000040>;	/* Internal registers */
315 			ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000
316 				  0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
318 			/* Inbound 2GB range starting at 0 */
319 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
321 			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
324 				0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8