Lines Matching +full:next +full:- +full:level +full:- +full:cache
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
99 #address-cells = <1>;
100 #size-cells = <0>;
106 next-level-cache = <&L2_0>;
107 fsl,portid-mapping = <0x80000000>;
108 L2_0: l2-cache {
109 next-level-cache = <&cpc>;
116 next-level-cache = <&L2_1>;
117 fsl,portid-mapping = <0x40000000>;
118 L2_1: l2-cache {
119 next-level-cache = <&cpc>;
126 next-level-cache = <&L2_2>;
127 fsl,portid-mapping = <0x20000000>;
128 L2_2: l2-cache {
129 next-level-cache = <&cpc>;
136 next-level-cache = <&L2_3>;
137 fsl,portid-mapping = <0x10000000>;
138 L2_3: l2-cache {
139 next-level-cache = <&cpc>;