boot/dts/bluestone.dts

16 	dcr-parent = <&{/cpus/cpu@0}>;
26 		#size-cells = <0>;
28 		cpu@0 {
31 			reg = <0x00000000>;
32 			clock-frequency = <0>; /* Filled in by U-Boot */
33 			timebase-frequency = <0>; /* Filled in by U-Boot */
46 		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 		cell-index = <0>;
53 		dcr-reg = <0x0c0 0x009>;
54 		#address-cells = <0>;
55 		#size-cells = <0>;
63 		dcr-reg = <0x0d0 0x009>;
64 		#address-cells = <0>;
65 		#size-cells = <0>;
67 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
75 		dcr-reg = <0x0e0 0x009>;
76 		#address-cells = <0>;
77 		#size-cells = <0>;
79 		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
87 		dcr-reg = <0x0f0 0x009>;
88 		#address-cells = <0>;
89 		#size-cells = <0>;
91 		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
100 		reg = <4 0x00040000 0x8000>; /* 32K */
105 		dcr-reg = <0x00e 0x002>;
110 		dcr-reg = <0x00c 0x002>;
115 		dcr-reg = <0x020 0x008
116 			   0x030 0x008>;
128 		clock-frequency = <0>; /* Filled in by U-Boot */
132 			dcr-reg = <0x010 0x002>;
138 			dcr-reg = <0x180 0x062>;
141 			#address-cells = <0>;
142 			#size-cells = <0>;
144 			interrupts = <	/*TXEOB*/ 0x6 0x4
145 					/*RXEOB*/ 0x7 0x4
146 					/*SERR*/  0x3 0x4
147 					/*TXDE*/  0x4 0x4
148 					/*RXDE*/  0x5 0x4>;
155 			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
156 			clock-frequency = <0>; /* Filled in by U-Boot */
160 				dcr-reg = <0x012 0x002>;
163 				clock-frequency = <0>; /* Filled in by U-Boot */
165 				ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
166 				interrupts = <0x6 0x4>;
169 				nor_flash@0,0 {
172 					reg = <0x00000000 0x00000000 0x00400000>;
175 					partition@0 {
177 						reg = <0x00000000 0x00180000>;
181 						reg = <0x00180000 0x00020000>;
185 						reg = <0x001a0000 0x00060000>;
189 				ndfc@1,0 {
191 					reg = <0x00000003 0x00000000 0x00002000>;
192 					ccr = <0x00001000>;
193 					bank-settings = <0x80002222>;
201 						partition@0 {
203 							reg   = <0x00000000 0x00C00000>;
207 							reg   = <0x00C00000 0x00B00000>;
211 							reg   = <0x01700000 0x00E00000>;
215 							reg   = <0x02500000 0x08200000>;
219 							reg   = <0x0A700000 0x00B00000>;
223 							reg   = <0x0B200000 0x00D00000>;
227 							reg   = <0x0BF00000 0x00C00000>;
231 							reg   = <0x0CB00000 0x3500000>;
240 				reg = <0xef600300 0x00000008>;
241 				virtual-reg = <0xef600300>;
242 				clock-frequency = <0>; /* Filled in by U-Boot */
243 				current-speed = <0>; /* Filled in by U-Boot */
245 				interrupts = <0x1 0x4>;
251 				reg = <0xef600400 0x00000008>;
252 				virtual-reg = <0xef600400>;
253 				clock-frequency = <0>; /* Filled in by U-Boot */
254 				current-speed = <0>; /* Filled in by U-Boot */
256 				interrupts = <0x1 0x4>;
261 				reg = <0xef600700 0x00000014>;
263 				interrupts = <0x2 0x4>;
265 				#size-cells = <0>;
268 					reg = <0x68>;
270 					interrupts = <0x9 0x8>;
274 					reg = <0x4C>;
276 					interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
282 				reg = <0xef600800 0x00000014>;
284 				interrupts = <0x3 0x4>;
289 				reg = <0xef601500 0x00000008>;
295 				reg = <0xef601350 0x00000030>;
302 				interrupts = <0x0 0x1>;
304 				#address-cells = <0>;
305 				#size-cells = <0>;
306 				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
307 						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
308 				reg = <0xef600c00 0x000000c4>;
311 				mal-tx-channel = <0>;
312 				mal-rx-channel = <0>;
313 				cell-index = <0>;
318 				phy-map = <0x00000000>;
320 				rgmii-channel = <0>;
322 				tah-channel = <0>;
335 			port = <0x0>; /* port number */
336 			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
337 			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
338 			dcr-reg = <0x100 0x020>;
339 			sdr-base = <0x300>;
344 			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
345 				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
346 				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
348 			/* Inbound 2GB range starting at 0 */
349 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
351 			/* This drives busses 40 to 0x7f */
352 			bus-range = <0x40 0x7f>;
360 			 * The real slot is on idsel 0, so the swizzling is 1:1
362 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
365 				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
366 				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
367 				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;