1 // SPDX-License-Identifier: GPL-2.0-or-later
39 /* skip LDB - never unaligned (index) */
47 /* skip LDB - never unaligned (short) */
55 /* skip STB - never unaligned */
59 /* skip STBY - never unaligned */
60 /* skip STDBY - never unaligned */
99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))  argument
104 #define ERR_NOTHANDLED	-1
110 	unsigned long saddr = regs->ior;  in emulate_ldh()
114 	DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",   in emulate_ldh()
115 		regs->isr, regs->ior, toreg);  in emulate_ldh()
118 "	mtsp	%4, %%sr1\n"  in emulate_ldh()
119 "1:	ldbs	0(%%sr1,%3), %2\n"  in emulate_ldh()
120 "2:	ldbs	1(%%sr1,%3), %0\n"  in emulate_ldh()
121 "	depw	%2, 23, 24, %0\n"  in emulate_ldh()
122 "3:	\n"  in emulate_ldh()
123 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")  in emulate_ldh()
124 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")  in emulate_ldh()
126 	: "r" (saddr), "r" (regs->isr) );  in emulate_ldh()
128 	DPRINTF("val = " RFMT "\n", val);  in emulate_ldh()
131 		regs->gr[toreg] = val;  in emulate_ldh()
138 	unsigned long saddr = regs->ior;  in emulate_ldw()
142 	DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",   in emulate_ldw()
143 		regs->isr, regs->ior, toreg);  in emulate_ldw()
146 "	zdep	%4,28,2,%2\n"		/* r19=(ofs&3)*8 */  in emulate_ldw()
147 "	mtsp	%5, %%sr1\n"  in emulate_ldw()
148 "	depw	%%r0,31,2,%4\n"  in emulate_ldw()
149 "1:	ldw	0(%%sr1,%4),%0\n"  in emulate_ldw()
150 "2:	ldw	4(%%sr1,%4),%3\n"  in emulate_ldw()
151 "	subi	32,%2,%2\n"  in emulate_ldw()
152 "	mtctl	%2,11\n"  in emulate_ldw()
153 "	vshd	%0,%3,%0\n"  in emulate_ldw()
154 "3:	\n"  in emulate_ldw()
155 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")  in emulate_ldw()
156 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")  in emulate_ldw()
158 	: "r" (saddr), "r" (regs->isr) );  in emulate_ldw()
160 	DPRINTF("val = " RFMT "\n", val);  in emulate_ldw()
163 		((__u32*)(regs->fr))[toreg] = val;  in emulate_ldw()
165 		regs->gr[toreg] = val;  in emulate_ldw()
171 	unsigned long saddr = regs->ior;  in emulate_ldd()
176 	DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",   in emulate_ldd()
177 		regs->isr, regs->ior, toreg);  in emulate_ldd()
184 "	depd,z	%2,60,3,%3\n"		/* shift=(ofs&7)*8 */  in emulate_ldd()
185 "	mtsp	%5, %%sr1\n"  in emulate_ldd()
186 "	depd	%%r0,63,3,%2\n"  in emulate_ldd()
187 "1:	ldd	0(%%sr1,%2),%0\n"  in emulate_ldd()
188 "2:	ldd	8(%%sr1,%2),%4\n"  in emulate_ldd()
189 "	subi	64,%3,%3\n"  in emulate_ldd()
190 "	mtsar	%3\n"  in emulate_ldd()
191 "	shrpd	%0,%4,%%sar,%0\n"  in emulate_ldd()
192 "3:	\n"  in emulate_ldd()
193 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")  in emulate_ldd()
194 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")  in emulate_ldd()
196 	: "r" (regs->isr) );  in emulate_ldd()
199 "	zdep	%2,29,2,%3\n"		/* shift=(ofs&3)*8 */  in emulate_ldd()
200 "	mtsp	%5, %%sr1\n"  in emulate_ldd()
201 "	dep	%%r0,31,2,%2\n"  in emulate_ldd()
202 "1:	ldw	0(%%sr1,%2),%0\n"  in emulate_ldd()
203 "2:	ldw	4(%%sr1,%2),%R0\n"  in emulate_ldd()
204 "3:	ldw	8(%%sr1,%2),%4\n"  in emulate_ldd()
205 "	subi	32,%3,%3\n"  in emulate_ldd()
206 "	mtsar	%3\n"  in emulate_ldd()
207 "	vshd	%0,%R0,%0\n"  in emulate_ldd()
208 "	vshd	%R0,%4,%R0\n"  in emulate_ldd()
209 "4:	\n"  in emulate_ldd()
212 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")  in emulate_ldd()
214 	: "r" (regs->isr) );  in emulate_ldd()
217 	DPRINTF("val = 0x%llx\n", val);  in emulate_ldd()
220 		regs->fr[toreg] = val;  in emulate_ldd()
222 		regs->gr[toreg] = val;  in emulate_ldd()
229 	unsigned long val = regs->gr[frreg], temp1;  in emulate_sth()
235 	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,  in emulate_sth()
236 		val, regs->isr, regs->ior);  in emulate_sth()
239 "	mtsp %4, %%sr1\n"  in emulate_sth()
240 "	extrw,u %2, 23, 8, %1\n"  in emulate_sth()
241 "1:	stb %1, 0(%%sr1, %3)\n"  in emulate_sth()
242 "2:	stb %2, 1(%%sr1, %3)\n"  in emulate_sth()
243 "3:	\n"  in emulate_sth()
244 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")  in emulate_sth()
245 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")  in emulate_sth()
247 	: "r" (val), "r" (regs->ior), "r" (regs->isr) );  in emulate_sth()
258 		val = ((__u32*)(regs->fr))[frreg];  in emulate_stw()
260 		val = regs->gr[frreg];  in emulate_stw()
264 	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,  in emulate_stw()
265 		val, regs->isr, regs->ior);  in emulate_stw()
269 "	mtsp %3, %%sr1\n"  in emulate_stw()
270 "	zdep	%2, 28, 2, %%r19\n"  in emulate_stw()
271 "	dep	%%r0, 31, 2, %2\n"  in emulate_stw()
272 "	mtsar	%%r19\n"  in emulate_stw()
273 "	depwi,z	-2, %%sar, 32, %%r19\n"  in emulate_stw()
274 "1:	ldw	0(%%sr1,%2),%%r20\n"  in emulate_stw()
275 "2:	ldw	4(%%sr1,%2),%%r21\n"  in emulate_stw()
276 "	vshd	%%r0, %1, %%r22\n"  in emulate_stw()
277 "	vshd	%1, %%r0, %%r1\n"  in emulate_stw()
278 "	and	%%r20, %%r19, %%r20\n"  in emulate_stw()
279 "	andcm	%%r21, %%r19, %%r21\n"  in emulate_stw()
280 "	or	%%r22, %%r20, %%r20\n"  in emulate_stw()
281 "	or	%%r1, %%r21, %%r21\n"  in emulate_stw()
282 "	stw	%%r20,0(%%sr1,%2)\n"  in emulate_stw()
283 "	stw	%%r21,4(%%sr1,%2)\n"  in emulate_stw()
284 "3:	\n"  in emulate_stw()
285 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")  in emulate_stw()
286 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")  in emulate_stw()
288 	: "r" (val), "r" (regs->ior), "r" (regs->isr)  in emulate_stw()
299 		val = regs->fr[frreg];  in emulate_std()
301 		val = regs->gr[frreg];  in emulate_std()
305 	DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,   in emulate_std()
306 		val,  regs->isr, regs->ior);  in emulate_std()
313 "	mtsp %3, %%sr1\n"  in emulate_std()
314 "	depd,z	%2, 60, 3, %%r19\n"  in emulate_std()
315 "	depd	%%r0, 63, 3, %2\n"  in emulate_std()
316 "	mtsar	%%r19\n"  in emulate_std()
317 "	depdi,z	-2, %%sar, 64, %%r19\n"  in emulate_std()
318 "1:	ldd	0(%%sr1,%2),%%r20\n"  in emulate_std()
319 "2:	ldd	8(%%sr1,%2),%%r21\n"  in emulate_std()
320 "	shrpd	%%r0, %1, %%sar, %%r22\n"  in emulate_std()
321 "	shrpd	%1, %%r0, %%sar, %%r1\n"  in emulate_std()
322 "	and	%%r20, %%r19, %%r20\n"  in emulate_std()
323 "	andcm	%%r21, %%r19, %%r21\n"  in emulate_std()
324 "	or	%%r22, %%r20, %%r20\n"  in emulate_std()
325 "	or	%%r1, %%r21, %%r21\n"  in emulate_std()
326 "3:	std	%%r20,0(%%sr1,%2)\n"  in emulate_std()
327 "4:	std	%%r21,8(%%sr1,%2)\n"  in emulate_std()
328 "5:	\n"  in emulate_std()
331 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")  in emulate_std()
334 	: "r" (val), "r" (regs->ior), "r" (regs->isr)  in emulate_std()
339 "	mtsp	%3, %%sr1\n"  in emulate_std()
340 "	zdep	%R1, 29, 2, %%r19\n"  in emulate_std()
341 "	dep	%%r0, 31, 2, %2\n"  in emulate_std()
342 "	mtsar	%%r19\n"  in emulate_std()
343 "	zvdepi	-2, 32, %%r19\n"  in emulate_std()
344 "1:	ldw	0(%%sr1,%2),%%r20\n"  in emulate_std()
345 "2:	ldw	8(%%sr1,%2),%%r21\n"  in emulate_std()
346 "	vshd	%1, %R1, %%r1\n"  in emulate_std()
347 "	vshd	%%r0, %1, %1\n"  in emulate_std()
348 "	vshd	%R1, %%r0, %R1\n"  in emulate_std()
349 "	and	%%r20, %%r19, %%r20\n"  in emulate_std()
350 "	andcm	%%r21, %%r19, %%r21\n"  in emulate_std()
351 "	or	%1, %%r20, %1\n"  in emulate_std()
352 "	or	%R1, %%r21, %R1\n"  in emulate_std()
353 "3:	stw	%1,0(%%sr1,%2)\n"  in emulate_std()
354 "4:	stw	%%r1,4(%%sr1,%2)\n"  in emulate_std()
355 "5:	stw	%R1,8(%%sr1,%2)\n"  in emulate_std()
356 "6:	\n"  in emulate_std()
359 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")  in emulate_std()
363 	: "r" (val), "r" (regs->ior), "r" (regs->isr)  in emulate_std()
374 	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;  in handle_unaligned()
382 		if (current->thread.flags & PARISC_UAC_SIGBUS) {  in handle_unaligned()
386 		if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&  in handle_unaligned()
389 				" at ip " RFMT " (iir " RFMT ")\n",  in handle_unaligned()
390 				current->comm, task_pid_nr(current), regs->ior,  in handle_unaligned()
391 				regs->iaoq[0], regs->iir);  in handle_unaligned()
401 	/* handle modification - OK, it's ugly, see the instruction manual */  in handle_unaligned()
402 	switch (MAJOR_OP(regs->iir))  in handle_unaligned()
407 		if (regs->iir&0x20)  in handle_unaligned()
410 			if (regs->iir&0x1000)		/* short loads */  in handle_unaligned()
411 				if (regs->iir&0x200)  in handle_unaligned()
412 					newbase += IM5_3(regs->iir);  in handle_unaligned()
414 					newbase += IM5_2(regs->iir);  in handle_unaligned()
415 			else if (regs->iir&0x2000)	/* scaled indexed */  in handle_unaligned()
418 				switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
426 					shift= 3; break;  in handle_unaligned()
428 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;  in handle_unaligned()
430 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);  in handle_unaligned()
436 		newbase += IM14(regs->iir);  in handle_unaligned()
440 		if (regs->iir&8)  in handle_unaligned()
443 			newbase += IM14(regs->iir&~0xe);  in handle_unaligned()
449 		newbase += IM14(regs->iir&6);  in handle_unaligned()
453 		if (regs->iir&4)  in handle_unaligned()
456 			newbase += IM14(regs->iir&~4);  in handle_unaligned()
462 	switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
466 		ret = emulate_ldh(regs, R3(regs->iir));  in handle_unaligned()
473 		ret = emulate_ldw(regs, R3(regs->iir), 0);  in handle_unaligned()
477 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
482 		ret = emulate_stw(regs, R2(regs->iir), 0);  in handle_unaligned()
490 		ret = emulate_ldd(regs, R3(regs->iir), 0);  in handle_unaligned()
495 		ret = emulate_std(regs, R2(regs->iir), 0);  in handle_unaligned()
503 		ret = emulate_ldw(regs, FR3(regs->iir), 1);  in handle_unaligned()
508 		ret = emulate_ldd(regs, R3(regs->iir), 1);  in handle_unaligned()
515 		ret = emulate_stw(regs, FR3(regs->iir), 1);  in handle_unaligned()
520 		ret = emulate_std(regs, R3(regs->iir), 1);  in handle_unaligned()
530 	switch (regs->iir & OPCODE2_MASK)  in handle_unaligned()
533 		ret = emulate_ldd(regs,R2(regs->iir),1);  in handle_unaligned()
536 		ret = emulate_std(regs, R2(regs->iir),1);  in handle_unaligned()
540 		ret = emulate_ldd(regs, R2(regs->iir),0);  in handle_unaligned()
543 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
547 	switch (regs->iir & OPCODE3_MASK)  in handle_unaligned()
550 		ret = emulate_ldw(regs, R2(regs->iir), 1);  in handle_unaligned()
553 		ret = emulate_ldw(regs, R2(regs->iir), 0);  in handle_unaligned()
557 		ret = emulate_stw(regs, R2(regs->iir),1);  in handle_unaligned()
560 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
563 	switch (regs->iir & OPCODE4_MASK)  in handle_unaligned()
566 		ret = emulate_ldh(regs, R2(regs->iir));  in handle_unaligned()
570 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
573 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
577 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
581 	if (ret == 0 && modify && R1(regs->iir))  in handle_unaligned()
582 		regs->gr[R1(regs->iir)] = newbase;  in handle_unaligned()
586 		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);  in handle_unaligned()
588 	DPRINTF("ret = %d\n", ret);  in handle_unaligned()
600 		printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);  in handle_unaligned()
603 		if (ret == -EFAULT)  in handle_unaligned()
606 					(void __user *)regs->ior);  in handle_unaligned()
613 					(void __user *)regs->ior);  in handle_unaligned()
620 	regs->gr[0]|=PSW_N;  in handle_unaligned()
636 	switch (regs->iir & OPCODE1_MASK) {  in check_unaligned()
650 		align_mask = 3UL;  in check_unaligned()
654 		switch (regs->iir & OPCODE4_MASK) {  in check_unaligned()
663 			align_mask = 3UL;  in check_unaligned()
669 	return (int)(regs->ior & align_mask);  in check_unaligned()