Lines Matching refs:l
30 l.movhi rd,hi(-KERNELBASE) ;\
31 l.add rd,rd,rs
34 l.movhi gpr,0x0
37 l.movhi gpr,hi(symbol) ;\
38 l.ori gpr,gpr,lo(symbol)
54 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
97 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
98 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
100 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
101 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
103 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
104 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
106 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
107 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
109 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
110 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
135 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
136 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
138 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
139 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
141 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
142 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
160 l.mfspr t1,r0,SPR_COREID ;\
161 l.slli t1,t1,2 ;\
162 l.add reg,reg,t1 ;\
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
177 l.mfspr r10,r0,SPR_COREID ;\
178 l.slli r10,r10,2 ;\
179 l.add r30,r30,r10 ;\
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
223 l.mfspr r30,r0,SPR_ESR_BASE ;\
224 l.andi r30,r30,SPR_SR_SM ;\
225 l.sfeqi r30,0 ;\
227 l.bnf 2f /* kernel_mode */ ;\
232 l.lwz r1,(TI_KSP)(r30) ;\
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
241 l.sw PT_GPR12(r30),r12 ;\
243 l.mfspr r12,r0,SPR_EPCR_BASE ;\
244 l.sw PT_PC(r30),r12 ;\
245 l.mfspr r12,r0,SPR_ESR_BASE ;\
246 l.sw PT_SR(r30),r12 ;\
249 l.sw PT_GPR30(r30),r12 ;\
252 l.sw PT_GPR10(r30),r12 ;\
255 l.sw PT_SP(r30),r12 ;\
257 l.sw PT_GPR4(r30),r4 ;\
258 l.mfspr r4,r0,SPR_EEAR_BASE ;\
263 l.mfspr r30,r0,SPR_SR ;\
264 l.andi r30,r30,SPR_SR_DSX ;\
265 l.ori r30,r30,(EXCEPTION_SR) ;\
266 l.mtspr r0,r30,SPR_ESR_BASE ;\
269 l.mtspr r0,r30,SPR_EPCR_BASE ;\
270 l.rfe
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
302 l.jal _emergency_print ;\
303 l.nop ;\
304 l.mfspr r3,r0,SPR_NPC ;\
305 l.jal _emergency_print_nr ;\
306 l.andi r3,r3,0x1f00 ;\
309 l.jal _emergency_print ;\
310 l.nop ;\
311 l.jal _emergency_print_nr ;\
312 l.mfspr r3,r0,SPR_EPCR_BASE ;\
315 l.jal _emergency_print ;\
316 l.nop ;\
318 l.addi r3,r1,0x0 ;\
319 l.addi r9,r10,0x0 ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
329 l.sw PT_GPR12(r30),r12 ;\
330 l.mfspr r12,r0,SPR_EPCR_BASE ;\
331 l.sw PT_PC(r30),r12 ;\
332 l.mfspr r12,r0,SPR_ESR_BASE ;\
333 l.sw PT_SR(r30),r12 ;\
336 l.sw PT_GPR30(r30),r12 ;\
339 l.sw PT_GPR10(r30),r12 ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
346 l.sw PT_GPR4(r30),r4 ;\
347 l.mfspr r4,r0,SPR_EEAR_BASE ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
352 l.mtspr r0,r30,SPR_ESR_BASE ;\
355 l.mtspr r0,r30,SPR_EPCR_BASE ;\
356 l.rfe
367 l.jr r13
368 l.nop
411 l.j boot_dtlb_miss_handler
412 l.nop
416 l.j boot_itlb_miss_handler
417 l.nop
519 l.or r25,r0,r3 /* pointer to fdt */
525 l.ori r3,r0,0x1
526 l.mtspr r0,r3,SPR_SR
534 l.movhi r3,hi(SPR_TTMR_CR)
535 l.mtspr r0,r3,SPR_TTMR
569 l.mfspr r26,r0,SPR_COREID
570 l.sfeq r26,r0
571 l.bnf secondary_wait
572 l.nop
581 l.sw TI_KSP(r31), r1
583 l.ori r4,r0,0x0
598 l.sw (0)(r28),r0
599 l.sfltu r28,r30
600 l.bf 1b
601 l.addi r28,r28,4
604 l.jal _ic_enable
605 l.nop
608 l.jal _dc_enable
609 l.nop
612 l.jal _flush_tlb
613 l.nop
622 l.mfspr r30,r0,SPR_SR
623 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
624 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
625 l.or r30,r30,r28
626 l.mtspr r0,r30,SPR_SR
627 l.nop
628 l.nop
629 l.nop
630 l.nop
631 l.nop
632 l.nop
633 l.nop
634 l.nop
635 l.nop
636 l.nop
637 l.nop
638 l.nop
639 l.nop
640 l.nop
641 l.nop
642 l.nop
645 l.nop 5
648 l.lwz r3,0(r25) /* load magic from fdt into r3 */
649 l.movhi r4,hi(OF_DT_HEADER)
650 l.ori r4,r4,lo(OF_DT_HEADER)
651 l.sfeq r3,r4
652 l.bf _fdt_found
653 l.nop
655 l.or r25,r0,r0
658 l.or r3,r0,r25
660 l.jalr r24
661 l.nop
702 l.jr r30
703 l.nop
711 l.addi r7,r0,128 /* Maximum number of sets */
713 l.mtspr r5,r0,0x0
714 l.mtspr r6,r0,0x0
716 l.addi r5,r5,1
717 l.addi r6,r6,1
718 l.sfeq r7,r0
719 l.bnf 1b
720 l.addi r7,r7,-1
722 l.jr r9
723 l.nop
729 l.mfspr r25,r0,SPR_UPR
730 l.andi r25,r25,SPR_UPR_PMP
731 l.sfeq r25,r0
732 l.bf secondary_check_release
733 l.nop
738 l.mtspr r0,r25,SPR_EVBAR
741 l.mfspr r25,r0,SPR_SR
742 l.ori r25,r25,SPR_SR_IEE
743 l.mtspr r0,r25,SPR_SR
746 l.mfspr r25,r0,SPR_PICMR
747 l.ori r25,r25,0xffff
748 l.mtspr r0,r25,SPR_PICMR
751 l.mfspr r25,r0,SPR_PMR
753 l.or r25,r25,r3
754 l.mtspr r0,r25,SPR_PMR
757 l.mtspr r0,r0,SPR_EVBAR
764 l.mfspr r25,r0,SPR_COREID
767 l.lwz r3,0(r4)
768 l.sfeq r25,r3
769 l.bnf secondary_wait
770 l.nop
779 l.lwz r10,0(r30)
780 l.addi r1,r10,THREAD_SIZE
782 l.sw TI_KSP(r30),r1
784 l.jal _ic_enable
785 l.nop
787 l.jal _dc_enable
788 l.nop
790 l.jal _flush_tlb
791 l.nop
796 l.mfspr r30,r0,SPR_SR
797 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
798 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
799 l.or r30,r30,r28
807 l.mtspr r0,r30,SPR_ESR_BASE
809 l.mtspr r0,r30,SPR_EPCR_BASE
810 l.rfe
814 l.jr r30
815 l.nop
828 l.mfspr r24,r0,SPR_UPR
829 l.andi r26,r24,SPR_UPR_ICP
830 l.sfeq r26,r0
831 l.bf 9f
832 l.nop
835 l.mfspr r6,r0,SPR_SR
836 l.addi r5,r0,-1
837 l.xori r5,r5,SPR_SR_ICE
838 l.and r5,r6,r5
839 l.mtspr r0,r5,SPR_SR
846 l.mfspr r24,r0,SPR_ICCFGR
847 l.andi r26,r24,SPR_ICCFGR_CBS
848 l.srli r28,r26,7
849 l.ori r30,r0,16
850 l.sll r14,r30,r28
856 l.andi r26,r24,SPR_ICCFGR_NCS
857 l.srli r28,r26,3
858 l.ori r30,r0,1
859 l.sll r16,r30,r28
862 l.addi r6,r0,0
863 l.sll r5,r14,r28
868 l.mtspr r0,r6,SPR_ICBIR
869 l.sfne r6,r5
870 l.bf 1b
871 l.add r6,r6,r14
875 l.mfspr r6,r0,SPR_SR
876 l.ori r6,r6,SPR_SR_ICE
877 l.mtspr r0,r6,SPR_SR
878 l.nop
879 l.nop
880 l.nop
881 l.nop
882 l.nop
883 l.nop
884 l.nop
885 l.nop
886 l.nop
887 l.nop
889 l.jr r9
890 l.nop
894 l.mfspr r24,r0,SPR_UPR
895 l.andi r26,r24,SPR_UPR_DCP
896 l.sfeq r26,r0
897 l.bf 9f
898 l.nop
901 l.mfspr r6,r0,SPR_SR
902 l.addi r5,r0,-1
903 l.xori r5,r5,SPR_SR_DCE
904 l.and r5,r6,r5
905 l.mtspr r0,r5,SPR_SR
912 l.mfspr r24,r0,SPR_DCCFGR
913 l.andi r26,r24,SPR_DCCFGR_CBS
914 l.srli r28,r26,7
915 l.ori r30,r0,16
916 l.sll r14,r30,r28
922 l.andi r26,r24,SPR_DCCFGR_NCS
923 l.srli r28,r26,3
924 l.ori r30,r0,1
925 l.sll r16,r30,r28
928 l.addi r6,r0,0
929 l.sll r5,r14,r28
931 l.mtspr r0,r6,SPR_DCBIR
932 l.sfne r6,r5
933 l.bf 1b
934 l.add r6,r6,r14
937 l.mfspr r6,r0,SPR_SR
938 l.ori r6,r6,SPR_SR_DCE
939 l.mtspr r0,r6,SPR_SR
941 l.jr r9
942 l.nop
983 l.mfspr r6,r0,SPR_ESR_BASE //
984 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
985 l.sfeqi r6,0 // r6 == 0x1 --> SM
986 l.bf exit_with_no_dtranslation //
987 l.nop
1000 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1005 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1007 l.mfspr r6, r0, SPR_DMMUCFGR
1008 l.andi r6, r6, SPR_DMMUCFGR_NTS
1009 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1010 l.ori r5, r0, 0x1
1011 l.sll r5, r5, r6 // r5 = number DMMU sets
1012 l.addi r6, r5, -1 // r6 = nsets mask
1013 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1015 l.or r6,r6,r4 // r6 <- r4
1016 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1017 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1018 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1019 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1020 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1024 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1025 l.bf 1f // goto out
1026 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1030 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1031 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1032 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1033 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1034 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1042 l.rfe // SR <- ESR, PC <- EPC
1048 l.j _dispatch_bus_fault
1079 l.mfspr r6,r0,SPR_ESR_BASE //
1080 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1081 l.sfeqi r6,0 // r6 == 0x1 --> SM
1082 l.bf exit_with_no_itranslation
1083 l.nop
1087 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1092 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1094 l.mfspr r6, r0, SPR_IMMUCFGR
1095 l.andi r6, r6, SPR_IMMUCFGR_NTS
1096 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1097 l.ori r5, r0, 0x1
1098 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1099 l.addi r6, r5, -1 // r6 = nsets mask
1100 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1102 l.or r6,r6,r4 // r6 <- r4
1103 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1104 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1105 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1106 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1107 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1117 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1118 l.bf 1f // goto out
1119 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1123 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1124 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1125 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1126 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1127 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1135 l.rfe // SR <- ESR, PC <- EPC
1140 l.j _dispatch_bus_fault
1141 l.nop
1166 l.mfspr r2,r0,SPR_EEAR_BASE
1171 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1172 l.slli r4,r4,0x2 // to get address << 2
1173 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1179 l.lwz r3,0x0(r4) // get *pmd value
1180 l.sfne r3,r0
1181 l.bnf d_pmd_none
1182 l.addi r3,r0,0xffffe000 // PAGE_MASK
1188 l.lwz r4,0x0(r4) // get **pmd value
1189 l.and r4,r4,r3 // & PAGE_MASK
1190 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1191 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1192 l.slli r3,r3,0x2 // to get address << 2
1193 l.add r3,r3,r4
1194 l.lwz r3,0x0(r3) // this is pte at last
1198 l.andi r4,r3,0x1
1199 l.sfne r4,r0 // is pte present
1200 l.bnf d_pte_not_present
1201 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1205 l.and r4,r3,r4 // apply the mask
1207 l.mfspr r2, r0, SPR_DMMUCFGR
1208 l.andi r2, r2, SPR_DMMUCFGR_NTS
1209 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1210 l.ori r3, r0, 0x1
1211 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1212 l.addi r2, r3, -1 // r2 = nsets mask
1213 l.mfspr r3, r0, SPR_EEAR_BASE
1214 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1215 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1217 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1221 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1222 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1223 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1228 l.rfe
1244 l.mfspr r2,r0,SPR_EEAR_BASE
1251 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1252 l.slli r4,r4,0x2 // to get address << 2
1253 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1259 l.lwz r3,0x0(r4) // get *pmd value
1260 l.sfne r3,r0
1261 l.bnf i_pmd_none
1262 l.addi r3,r0,0xffffe000 // PAGE_MASK
1269 l.lwz r4,0x0(r4) // get **pmd value
1270 l.and r4,r4,r3 // & PAGE_MASK
1271 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1272 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1273 l.slli r3,r3,0x2 // to get address << 2
1274 l.add r3,r3,r4
1275 l.lwz r3,0x0(r3) // this is pte at last
1280 l.andi r4,r3,0x1
1281 l.sfne r4,r0 // is pte present
1282 l.bnf i_pte_not_present
1283 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1287 l.and r4,r3,r4 // apply the mask
1288 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1289 l.sfeq r3,r0
1290 l.bf itlb_tr_fill //_workaround
1292 l.mfspr r2, r0, SPR_IMMUCFGR
1293 l.andi r2, r2, SPR_IMMUCFGR_NTS
1294 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1295 l.ori r3, r0, 0x1
1296 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1297 l.addi r2, r3, -1 // r2 = nsets mask
1298 l.mfspr r3, r0, SPR_EEAR_BASE
1299 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1300 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1310 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1312 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1316 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1317 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1318 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1323 l.rfe
1355 l.movhi r4,hi(UART_BASE_ADD)
1356 l.ori r4,r4,lo(UART_BASE_ADD)
1360 1: l.lwz r5,4(r4)
1361 l.andi r5,r5,0xff
1362 l.sfnei r5,0
1363 l.bf 1b
1364 l.nop
1367 l.andi r7,r7,0xff
1368 l.sw 0(r4),r7
1371 l.addi r6,r0,0x20
1372 1: l.lbz r5,5(r4)
1373 l.andi r5,r5,0x20
1374 l.sfeq r5,r6
1375 l.bnf 1b
1376 l.nop
1379 l.sb 0(r4),r7
1382 l.addi r6,r0,0x60
1383 1: l.lbz r5,5(r4)
1384 l.andi r5,r5,0x60
1385 l.sfeq r5,r6
1386 l.bnf 1b
1387 l.nop
1392 l.jr r9
1393 l.nop
1410 2: l.lbz r7,0(r3)
1411 l.sfeqi r7,0x0
1412 l.bf 9f
1413 l.nop
1415 l.jal _emergency_putc
1416 l.nop
1419 l.j 2b
1420 l.addi r3,r3,0x1
1425 l.jr r9
1426 l.nop
1442 l.addi r8,r0,32 // shift register
1445 l.addi r8,r8,-0x4
1446 l.srl r7,r3,r8
1447 l.andi r7,r7,0xf
1450 l.sfeqi r8,0x4
1451 l.bf 2f
1452 l.nop
1454 l.sfeq r7,r0
1455 l.bf 1b
1456 l.nop
1459 l.srl r7,r3,r8
1461 l.andi r7,r7,0xf
1462 l.sflts r8,r0
1463 l.bf 9f
1466 l.sfgtui r7,0x9
1467 l.bnf 8f
1468 l.nop
1469 l.addi r7,r7,0x27
1472 8: l.jal _emergency_putc
1473 l.addi r7,r7,0x30
1476 l.j 2b
1477 l.addi r8,r8,-0x4
1483 l.jr r9
1484 l.nop
1508 l.movhi r3,hi(UART_BASE_ADD)
1509 l.ori r3,r3,lo(UART_BASE_ADD)
1512 l.addi r4,r0,0x7
1513 l.sb 0x2(r3),r4
1515 l.addi r4,r0,0x0
1516 l.sb 0x1(r3),r4
1518 l.addi r4,r0,0x3
1519 l.sb 0x3(r3),r4
1521 l.lbz r5,3(r3)
1522 l.ori r4,r5,0x80
1523 l.sb 0x3(r3),r4
1524 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1525 l.sb UART_DLM(r3),r4
1526 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1527 l.sb UART_DLL(r3),r4
1528 l.sb 0x3(r3),r5
1531 l.jr r9
1532 l.nop
1540 l.ori r3,r0,SPR_SR_SM
1541 l.mtspr r0,r3,SPR_ESR_BASE
1542 l.rfe