858 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
868 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
876 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
887 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
898 	if (MIPSInst_RT(ir))  in cop1_cfc()
899 		xcp->regs[MIPSInst_RT(ir)] = value;  in cop1_cfc()
912 	if (MIPSInst_RT(ir) == 0)  in cop1_ctc()
915 		value = xcp->regs[MIPSInst_RT(ir)];  in cop1_ctc()
920 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
931 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
942 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
951 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
1064 		DITOREG(dval, MIPSInst_RT(ir));  in cop1Emulate()
1071 		DIFROMREG(dval, MIPSInst_RT(ir));  in cop1Emulate()
1098 		SITOREG(wval, MIPSInst_RT(ir));  in cop1Emulate()
1105 		SIFROMREG(wval, MIPSInst_RT(ir));  in cop1Emulate()
1125 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1126 				DIFROMREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1136 			DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1144 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1145 				SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1155 			SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1160 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1161 				SIFROMREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1168 			SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1191 			fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];  in cop1Emulate()
1210 				cbit = fpucondbit[MIPSInst_RT(ir) >> 2];  in cop1Emulate()
1216 			switch (MIPSInst_RT(ir) & 3) {  in cop1Emulate()
1374 		cond = fpucondbit[MIPSInst_RT(ir) >> 2];  in cop1Emulate()
1375 		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))  in cop1Emulate()