Lines Matching refs:DIVIL_MSR_REG
18 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
19 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
20 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
59 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_enable()
61 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_enable()
74 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); in divil_lbar_disable()
76 _wrmsr(DIVIL_MSR_REG(offset), hi, lo); in divil_lbar_disable()
194 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); in pci_isa_write_reg()
199 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); in pci_isa_write_reg()
202 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); in pci_isa_write_reg()
207 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); in pci_isa_write_reg()
241 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); in pci_isa_read_reg()