Lines Matching refs:kvm_restore_msa_upper

93 	.macro	kvm_restore_msa_upper	wr, off, base  macro
114 	kvm_restore_msa_upper	0,  VCPU_FPR0 +8, a0
115 	kvm_restore_msa_upper	1,  VCPU_FPR1 +8, a0
116 	kvm_restore_msa_upper	2,  VCPU_FPR2 +8, a0
117 	kvm_restore_msa_upper	3,  VCPU_FPR3 +8, a0
118 	kvm_restore_msa_upper	4,  VCPU_FPR4 +8, a0
119 	kvm_restore_msa_upper	5,  VCPU_FPR5 +8, a0
120 	kvm_restore_msa_upper	6,  VCPU_FPR6 +8, a0
121 	kvm_restore_msa_upper	7,  VCPU_FPR7 +8, a0
122 	kvm_restore_msa_upper	8,  VCPU_FPR8 +8, a0
123 	kvm_restore_msa_upper	9,  VCPU_FPR9 +8, a0
124 	kvm_restore_msa_upper	10, VCPU_FPR10+8, a0
125 	kvm_restore_msa_upper	11, VCPU_FPR11+8, a0
126 	kvm_restore_msa_upper	12, VCPU_FPR12+8, a0
127 	kvm_restore_msa_upper	13, VCPU_FPR13+8, a0
128 	kvm_restore_msa_upper	14, VCPU_FPR14+8, a0
129 	kvm_restore_msa_upper	15, VCPU_FPR15+8, a0
130 	kvm_restore_msa_upper	16, VCPU_FPR16+8, a0
131 	kvm_restore_msa_upper	17, VCPU_FPR17+8, a0
132 	kvm_restore_msa_upper	18, VCPU_FPR18+8, a0
133 	kvm_restore_msa_upper	19, VCPU_FPR19+8, a0
134 	kvm_restore_msa_upper	20, VCPU_FPR20+8, a0
135 	kvm_restore_msa_upper	21, VCPU_FPR21+8, a0
136 	kvm_restore_msa_upper	22, VCPU_FPR22+8, a0
137 	kvm_restore_msa_upper	23, VCPU_FPR23+8, a0
138 	kvm_restore_msa_upper	24, VCPU_FPR24+8, a0
139 	kvm_restore_msa_upper	25, VCPU_FPR25+8, a0
140 	kvm_restore_msa_upper	26, VCPU_FPR26+8, a0
141 	kvm_restore_msa_upper	27, VCPU_FPR27+8, a0
142 	kvm_restore_msa_upper	28, VCPU_FPR28+8, a0
143 	kvm_restore_msa_upper	29, VCPU_FPR29+8, a0
144 	kvm_restore_msa_upper	30, VCPU_FPR30+8, a0
145 	kvm_restore_msa_upper	31, VCPU_FPR31+8, a0