1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
32 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)  in core_vpe_count()  argument
34 	return min(smp_max_threads, mips_cps_numvps(cluster, core));  in core_vpe_count()
60 			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */  in cps_smp_setup()
64 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {  in cps_smp_setup()
88 	/* Core 0 is powered up (we're running on it) */  in cps_smp_setup()
91 	/* Initialise core 0 */  in cps_smp_setup()
94 	/* Make core 0 coherent with everything */  in cps_smp_setup()
103 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_setup()
117 	/* Detect whether the CCA is unsuited to multi-core SMP */  in cps_prepare_cpus()
122 		/* The CCA is coherent, multi-core is fine */  in cps_prepare_cpus()
127 		/* CCA is not coherent, multi-core is not usable */  in cps_prepare_cpus()
131 	/* Warn the user if the CCA prevents multi-core */  in cps_prepare_cpus()
143 		pr_warn("Using only one core due to %s%s%s\n",  in cps_prepare_cpus()
160 		     (void *)entry_code - (void *)&mips_cps_core_entry);  in cps_prepare_cpus()
163 	/* Allocate core boot configuration structs */  in cps_prepare_cpus()
207 static void boot_core(unsigned int core, unsigned int vpe_id)  in boot_core()  argument
212 	/* Select the appropriate core */  in boot_core()
213 	mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in boot_core()
224 	/* Ensure the core can access the GCRs */  in boot_core()
226 		set_gcr_access(1 << core);  in boot_core()
228 		set_gcr_access_cm3(1 << core);  in boot_core()
231 		/* Reset the core */  in boot_core()
232 		mips_cpc_lock_other(core);  in boot_core()
241 			 * core leaves reset.  in boot_core()
254 			/* U6 == coherent execution, ie. the core is up */  in boot_core()
260 				timeout--;  in boot_core()
265 			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",  in boot_core()
266 				core, stat);  in boot_core()
272 		/* Take the core out of reset */  in boot_core()
278 	/* The core is now powered up */  in boot_core()
279 	bitmap_set(core_power, core, 1);  in boot_core()
284 	unsigned core = cpu_core(&current_cpu_data);  in remote_vpe_boot()  local
285 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];  in remote_vpe_boot()
292 	unsigned core = cpu_core(&cpu_data[cpu]);  in cps_boot_secondary()  local
294 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];  in cps_boot_secondary()
295 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];  in cps_boot_secondary()
302 		return -ENOSYS;  in cps_boot_secondary()
304 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;  in cps_boot_secondary()
305 	vpe_cfg->sp = __KSTK_TOS(idle);  in cps_boot_secondary()
306 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);  in cps_boot_secondary()
308 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);  in cps_boot_secondary()
312 	if (!test_bit(core, core_power)) {  in cps_boot_secondary()
313 		/* Boot a VPE on a powered down core */  in cps_boot_secondary()
314 		boot_core(core, vpe_id);  in cps_boot_secondary()
319 		mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_boot_secondary()
326 		/* Boot a VPE on another powered up core */  in cps_boot_secondary()
334 			pr_crit("No online CPU in core %u to start CPU%d\n",  in cps_boot_secondary()
335 				core, cpu);  in cps_boot_secondary()
348 	/* Boot a VPE on this core */  in cps_boot_secondary()
357 	int core = cpu_core(&current_cpu_data);  in cps_init_secondary()  local
359 	/* Disable MT - we only want to run 1 TC per VPE */  in cps_init_secondary()
374 	if (core > 0 && !read_gcr_cl_coherence())  in cps_init_secondary()
375 		pr_warn("Core %u is not in coherent domain\n", core);  in cps_init_secondary()
390 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_finish()
407 	unsigned int cpu, core, vpe_id;  in cps_shutdown_this_cpu()  local
410 	core = cpu_core(&cpu_data[cpu]);  in cps_shutdown_this_cpu()
415 		pr_debug("Halting core %d VP%d\n", core, vpe_id);  in cps_shutdown_this_cpu()
428 			pr_debug("Gating power to core %d\n", core);  in cps_shutdown_this_cpu()
429 			/* Power down the core */  in cps_shutdown_this_cpu()
457 		return -EINVAL;  in cps_cpu_disable()
460 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);  in cps_cpu_disable()
484 		/* Look for another online VPE within the core */  in play_dead()
490 			 * There is an online VPE within the core. Just halt  in play_dead()
491 			 * this TC and leave the core alone.  in play_dead()
525 	unsigned core = cpu_core(&cpu_data[cpu]);  in cps_cleanup_dead_cpu()  local
535 	 *   - Onlining the CPU again.  in cps_cleanup_dead_cpu()
536 	 *   - Powering down the core if another VPE within it is offlined.  in cps_cleanup_dead_cpu()
537 	 *   - A sibling VPE entering a non-coherent state.  in cps_cleanup_dead_cpu()
539 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing  in cps_cleanup_dead_cpu()
544 		 * Wait for the core to enter a powered down or clock gated  in cps_cleanup_dead_cpu()
546 		 * in which case the CPC will refuse to power down the core.  in cps_cleanup_dead_cpu()
550 			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_cleanup_dead_cpu()
551 			mips_cpc_lock_other(core);  in cps_cleanup_dead_cpu()
564 			 * The core ought to have powered down, but didn't &  in cps_cleanup_dead_cpu()
571 			 * the hope that the core is doing nothing harmful &  in cps_cleanup_dead_cpu()
580 		/* Indicate the core is powered off */  in cps_cleanup_dead_cpu()
581 		bitmap_clear(core_power, core, 1);  in cps_cleanup_dead_cpu()
594 			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_cleanup_dead_cpu()
631 		return -ENODEV;  in register_cps_smp_ops()
634 	/* check we have a GIC - we need one for IPIs */  in register_cps_smp_ops()
637 		return -ENODEV;  in register_cps_smp_ops()