Lines Matching refs:CNTR_ODD
62 #define CNTR_ODD 0xaaaaaaaa macro
939 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
940 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
942 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
948 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
949 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
951 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
955 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },
956 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },
958 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },
959 [PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },
960 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
961 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },
966 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
968 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
1000 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
1001 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
1002 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
1019 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1023 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1029 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1033 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1045 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1049 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1056 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1060 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1066 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1070 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1077 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1081 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1099 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1100 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1103 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1104 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1110 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1114 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1126 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1130 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1142 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1146 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1153 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1157 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1168 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1169 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1172 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1173 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1178 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1179 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1185 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1186 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1189 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1190 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1196 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1197 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1214 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1217 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1230 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1233 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1238 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1241 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1248 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1252 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1386 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1390 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1396 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1400 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1413 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1417 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1423 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1426 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1714 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1717 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1728 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1731 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1744 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1747 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1754 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1757 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1768 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1771 raw_id > 255 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1780 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1784 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1787 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1799 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1802 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1814 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; in mipsxx_pmu_map_raw_event()
1817 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()
1825 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; in mipsxx_pmu_map_raw_event()