mips/kernel/perf_event_mipsxx.c

63 	#define CNTR_ALL	0xffffffff  macro
972 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x80, CNTR_ALL },
973 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x81, CNTR_ALL },
974 	[PERF_COUNT_HW_CACHE_MISSES] = { 0x18, CNTR_ALL },
975 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x94, CNTR_ALL },
976 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x9c, CNTR_ALL },
980 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_ALL },
981 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_ALL },
982 	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x1c, CNTR_ALL },
983 	[PERF_COUNT_HW_CACHE_MISSES] = { 0x1d, CNTR_ALL },
984 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_ALL },
985 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x08, CNTR_ALL },
989 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
990 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
991 	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
992 	[PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL	 },
993 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
994 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
995 	[PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
1269 		[C(RESULT_ACCESS)]	= { 0x156, CNTR_ALL },
1272 		[C(RESULT_ACCESS)]	= { 0x155, CNTR_ALL },
1273 		[C(RESULT_MISS)]        = { 0x153, CNTR_ALL },
1278 		[C(RESULT_MISS)]	= { 0x18, CNTR_ALL },
1281 		[C(RESULT_MISS)]        = { 0x18, CNTR_ALL },
1286 		[C(RESULT_ACCESS)]	= { 0x1b6, CNTR_ALL },
1289 		[C(RESULT_ACCESS)]	= { 0x1b7, CNTR_ALL },
1292 		[C(RESULT_ACCESS)]	= { 0x1bf, CNTR_ALL },
1297 		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1300 		[C(RESULT_MISS)]        = { 0x92, CNTR_ALL },
1305 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1308 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1314 		[C(RESULT_ACCESS)]      = { 0x94, CNTR_ALL },
1315 		[C(RESULT_MISS)]        = { 0x9c, CNTR_ALL },
1332 		[C(RESULT_ACCESS)]      = { 0x1e, CNTR_ALL },
1333 		[C(RESULT_MISS)]        = { 0x1f, CNTR_ALL },
1336 		[C(RESULT_ACCESS)]	= { 0xaa, CNTR_ALL },
1337 		[C(RESULT_MISS)]	= { 0xa9, CNTR_ALL },
1342 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ALL },
1343 		[C(RESULT_MISS)]	= { 0x1d, CNTR_ALL },
1348 		[C(RESULT_ACCESS)]	= { 0x2e, CNTR_ALL },
1349 		[C(RESULT_MISS)]	= { 0x2f, CNTR_ALL },
1354 		[C(RESULT_ACCESS)]      = { 0x14, CNTR_ALL },
1355 		[C(RESULT_MISS)]	= { 0x1b, CNTR_ALL },
1360 		[C(RESULT_MISS)]	= { 0x1a, CNTR_ALL },
1366 		[C(RESULT_ACCESS)]      = { 0x02, CNTR_ALL },
1367 		[C(RESULT_MISS)]        = { 0x08, CNTR_ALL },
1437 		[C(RESULT_ACCESS)]	= { 0x2b, CNTR_ALL },
1438 		[C(RESULT_MISS)]	= { 0x2e, CNTR_ALL },
1441 		[C(RESULT_ACCESS)]	= { 0x30, CNTR_ALL },
1446 		[C(RESULT_ACCESS)]	= { 0x18, CNTR_ALL },
1449 		[C(RESULT_ACCESS)]	= { 0x19, CNTR_ALL },
1458 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1461 		[C(RESULT_MISS)]	= { 0x35, CNTR_ALL },
1466 		[C(RESULT_MISS)]	= { 0x37, CNTR_ALL },
1829 			raw_event.cntr_mask = CNTR_ALL;  in mipsxx_pmu_map_raw_event()
1843 			raw_event.cntr_mask = CNTR_ALL;  in mipsxx_pmu_map_raw_event()
1860 	raw_event.cntr_mask = CNTR_ALL;  in octeon_pmu_map_raw_event()