mips/kernel/cps-vec.S

176 1:	PTR_L	t1, VPEBOOTCFG_PC(v1)
179 	jr	t1
239 	PTR_LA	t1, 1f
240 	jr.hb	t1
270 	sll	t1, ta1, VPECONF0_XTC_SHIFT
271 	or	t0, t0, t1
307 	li	t1, COREBOOTCFG_SIZE
308 	mul	t0, t0, t1
309 	PTR_LA	t1, mips_cps_core_bootcfg
310 	PTR_L	t1, 0(t1)
311 	PTR_ADDU v0, t0, t1
329 	mfc0	t1, CP0_MVPCONF0
330 	srl	t1, t1, MVPCONF0_PVPE_SHIFT
331 	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
332 	addiu	t1, t1, 1
335 	clz	t1, t1
337 	subu	t1, t2, t1
339 	sll	t1, t2, t1
340 	addiu	t1, t1, -1
344 	and	t9, t9, t1
348 	li	t1, VPEBOOTCFG_SIZE
349 	mul	v1, t9, t1
366 	PTR_LA	t1, mips_gcr_base
367 	PTR_L	t1, 0(t1)
368 	PTR_L	t1, GCR_CPC_BASE_OFS(t1)
370 	and	t1, t1, t2
372 	PTR_ADD	t1, t1, t2
375 	PTR_S	ta2, CPC_CL_VC_RUN_OFS(t1)
379 	PTR_S	ta2, CPC_CL_VC_STOP_OFS(t1)
394 	PTR_LA	t1, 1f
395 	jr.hb	t1
397 1:	mfc0	t1, CP0_MVPCONTROL
398 	ori	t1, t1, MVPCONTROL_VPC
399 	mtc0	t1, CP0_MVPCONTROL
434 	lw	t1, VPEBOOTCFG_PC(t0)
435 	mttc0	t1, CP0_TCRESTART
438 	lw	t1, VPEBOOTCFG_SP(t0)
439 	mttgpr	t1, sp
442 	lw	t1, VPEBOOTCFG_GP(t0)
443 	mttgpr	t1, gp
470 	li	t1, ~TCSTATUS_IXMT
471 	and	t0, t0, t1
490 	mfc0	t1, CP0_MVPCONTROL
491 	xori	t1, t1, MVPCONTROL_VPC
492 	mtc0	t1, CP0_MVPCONTROL
541 	 li	t1, 2
542 	sllv	t0, t1, t0
545 	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
546 	xori	t2, t1, 0x7
549 	addiu	t1, t1, 1
550 	sllv	t1, t3, t1
551 1:	/* At this point t1 == I-cache sets per way */
554 	mul	t1, t1, t0
555 	mul	t1, t1, t2
558 	PTR_ADD	a1, a0, t1
568 	 li	t1, 2
569 	sllv	t0, t1, t0
572 	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
573 	xori	t2, t1, 0x7
576 	addiu	t1, t1, 1
577 	sllv	t1, t3, t1
578 1:	/* At this point t1 == D-cache sets per way */
581 	mul	t1, t1, t0
582 	mul	t1, t1, t2
585 	PTR_ADDU a1, a0, t1
616 	psstate	t1
624 	psstate	t1