mips/kernel/bmips_5xxx_init.S

65 #define CP0_D_SEC_CACHE_DATA_LO	$28, 3
75 #define CP0_BRCM_MODE_BrPRED_MASK 	(3 << 24)
83 #define BRCM_ZSC_CONFIG_REG			0 << 3
84 #define BRCM_ZSC_REQ_BUFFER_REG			2 << 3
85 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0		4 << 3
86 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG1		6 << 3
87 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2		8 << 3
89 #define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0		0xa << 3
90 #define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1		0xc << 3
92 #define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0		0xe << 3
93 #define BRCM_ZSC_SCB1_ADDR_MAPPING_REG1		0x10 << 3
113  * Trashes:	v0, v1, a0, t0
122 	mfc0	a0, CP0_CONFIG, 1
123 	move	t0, a0
134 	srl	a0, a0, IS_SHIFT
135 	and	a0, a0, IS_MASK
140 	sllv	v0, v0, a0
150 	move	a0, t0
152 	srl	a0, a0, IL_SHIFT
153 	and	a0, a0, IL_MASK
155 	beqz	a0, no_i_cache
160 	addi	a0, a0, 1
162 	sll	v1, v1, a0
168 	sll	v0, v0, a0
174 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
178 	move	a0, t0
180 	srl	a0, a0, IA_SHIFT
181 	and	a0, a0, IA_MASK
182 	addi	a0, a0, 0x1
188 	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
208  * Trashes:	v0, v1, a0, t0
215 	mfc0	a0, CP0_CONFIG, 1
216 	move	t0, a0
227 	srl	a0, a0, DS_SHIFT
228 	and	a0, a0, DS_MASK
233 	sllv	v0, v0, a0
242 	move	a0, t0
244 	srl	a0, a0, DL_SHIFT
245 	and	a0, a0, DL_MASK
247 	beqz	a0, no_d_cache
252 	addi	a0, a0, 1
254 	sll	v1, v1, a0
260 	sll	v0, v0, a0
265 	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
269 	move	a0, t0
271 	srl	a0, a0, DA_SHIFT
272 	and	a0, a0, DA_MASK
273 	addi	a0, a0, 0x1
279 	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
324  * Trashes:	a0, v0, v1, t0, t1, t2, t8
368 	or	t0, t0, 3	/* Write Back mode */
375 	li	a0, KSEG0
376 	cacheop(a0, v0, v1, Index_Store_Tag_I)
396 	li	a0, KSEG0
397 	cacheop(a0, v0, v1, Index_Store_Tag_D)
521  * Arguments:	set clock ratio specified by a0
524  * Trashes:	v0, v1, a0, a1
537 	or	t0, t0, a0
578  * Arguments:	a0=0 disable llmb, a0=1 enables llmb
597 	beqz	a0, svlmb
620  * Trashes:	v0,v1,a0,a1,t8
636 	li	a0, 1
656 	li	a0, 0
724 	/* save return address and A0 */
726 	move	t5, a0
739 	move 	a0, t5