Lines Matching refs:CVMX_CIU_ADDR
12 #define CVMX_CIU_ADDR(addr, coreid, coremask, offset) \ macro
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
25 #define CVMX_CIU_INTX_EN1_W1C(c) CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
26 #define CVMX_CIU_INTX_EN1_W1S(c) CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
27 #define CVMX_CIU_INTX_SUM0(c) CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
28 #define CVMX_CIU_NMI CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
29 #define CVMX_CIU_PCI_INTA CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
30 #define CVMX_CIU_PP_BIST_STAT CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
31 #define CVMX_CIU_PP_DBG CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
32 #define CVMX_CIU_PP_RST CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
33 #define CVMX_CIU_QLM0 CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
34 #define CVMX_CIU_QLM1 CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
35 #define CVMX_CIU_QLM_JTGC CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
36 #define CVMX_CIU_QLM_JTGD CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
37 #define CVMX_CIU_SOFT_BIST CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
38 #define CVMX_CIU_SOFT_PRST1 CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
39 #define CVMX_CIU_SOFT_PRST CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
40 #define CVMX_CIU_SOFT_RST CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
41 #define CVMX_CIU_SUM2_PPX_IP4(c) CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
42 #define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
43 #define CVMX_CIU_TIMX(c) CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
48 return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8); in CVMX_CIU_MBOX_CLRX()
50 return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8); in CVMX_CIU_MBOX_CLRX()
56 return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8); in CVMX_CIU_MBOX_SETX()
58 return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8); in CVMX_CIU_MBOX_SETX()
65 return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8); in CVMX_CIU_PP_POKEX()
69 return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) - in CVMX_CIU_PP_POKEX()
72 return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8); in CVMX_CIU_PP_POKEX()
80 return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8); in CVMX_CIU_WDOGX()
84 return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) - in CVMX_CIU_WDOGX()
87 return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8); in CVMX_CIU_WDOGX()