Lines Matching refs:_ULCAST_
36 #define _ULCAST_
39 #define _ULCAST_ (unsigned long) macro
137 #define ENTRYLO_G (_ULCAST_(1) << 0)
138 #define ENTRYLO_V (_ULCAST_(1) << 1)
139 #define ENTRYLO_D (_ULCAST_(1) << 2)
141 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
144 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
145 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
146 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
147 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
151 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
158 #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
160 #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
162 #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
223 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
225 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
243 #define PG_RIE (_ULCAST_(1) << 31)
244 #define PG_XIE (_ULCAST_(1) << 30)
245 #define PG_ELPA (_ULCAST_(1) << 29)
246 #define PG_ESP (_ULCAST_(1) << 28)
247 #define PG_IEC (_ULCAST_(1) << 27)
250 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
251 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
252 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
257 #define IE_SW0 (_ULCAST_(1) << 8)
258 #define IE_SW1 (_ULCAST_(1) << 9)
259 #define IE_IRQ0 (_ULCAST_(1) << 10)
260 #define IE_IRQ1 (_ULCAST_(1) << 11)
261 #define IE_IRQ2 (_ULCAST_(1) << 12)
262 #define IE_IRQ3 (_ULCAST_(1) << 13)
263 #define IE_IRQ4 (_ULCAST_(1) << 14)
264 #define IE_IRQ5 (_ULCAST_(1) << 15)
269 #define C_SW0 (_ULCAST_(1) << 8)
270 #define C_SW1 (_ULCAST_(1) << 9)
271 #define C_IRQ0 (_ULCAST_(1) << 10)
272 #define C_IRQ1 (_ULCAST_(1) << 11)
273 #define C_IRQ2 (_ULCAST_(1) << 12)
274 #define C_IRQ3 (_ULCAST_(1) << 13)
275 #define C_IRQ4 (_ULCAST_(1) << 14)
276 #define C_IRQ5 (_ULCAST_(1) << 15)
318 #define ST0_UM (_ULCAST_(1) << 4)
319 #define ST0_IL (_ULCAST_(1) << 23)
320 #define ST0_DL (_ULCAST_(1) << 24)
332 #define STATUSF_IP0 (_ULCAST_(1) << 8)
334 #define STATUSF_IP1 (_ULCAST_(1) << 9)
336 #define STATUSF_IP2 (_ULCAST_(1) << 10)
338 #define STATUSF_IP3 (_ULCAST_(1) << 11)
340 #define STATUSF_IP4 (_ULCAST_(1) << 12)
342 #define STATUSF_IP5 (_ULCAST_(1) << 13)
344 #define STATUSF_IP6 (_ULCAST_(1) << 14)
346 #define STATUSF_IP7 (_ULCAST_(1) << 15)
348 #define STATUSF_IP8 (_ULCAST_(1) << 0)
350 #define STATUSF_IP9 (_ULCAST_(1) << 1)
352 #define STATUSF_IP10 (_ULCAST_(1) << 2)
354 #define STATUSF_IP11 (_ULCAST_(1) << 3)
356 #define STATUSF_IP12 (_ULCAST_(1) << 4)
358 #define STATUSF_IP13 (_ULCAST_(1) << 5)
360 #define STATUSF_IP14 (_ULCAST_(1) << 6)
362 #define STATUSF_IP15 (_ULCAST_(1) << 7)
388 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
390 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
392 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
400 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
402 #define CAUSEF_IP (_ULCAST_(255) << 8)
404 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
406 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
408 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
410 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
412 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
414 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
416 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
418 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
420 #define CAUSEF_FDCI (_ULCAST_(1) << 21)
422 #define CAUSEF_WP (_ULCAST_(1) << 22)
424 #define CAUSEF_IV (_ULCAST_(1) << 23)
426 #define CAUSEF_PCI (_ULCAST_(1) << 26)
428 #define CAUSEF_DC (_ULCAST_(1) << 27)
430 #define CAUSEF_CE (_ULCAST_(3) << 28)
432 #define CAUSEF_TI (_ULCAST_(1) << 30)
434 #define CAUSEF_BD (_ULCAST_(1) << 31)
485 #define CONF_BE (_ULCAST_(1) << 15)
488 #define CONF_CU (_ULCAST_(1) << 3)
489 #define CONF_DB (_ULCAST_(1) << 4)
490 #define CONF_IB (_ULCAST_(1) << 5)
491 #define CONF_DC (_ULCAST_(7) << 6)
492 #define CONF_IC (_ULCAST_(7) << 9)
493 #define CONF_EB (_ULCAST_(1) << 13)
494 #define CONF_EM (_ULCAST_(1) << 14)
495 #define CONF_SM (_ULCAST_(1) << 16)
496 #define CONF_SC (_ULCAST_(1) << 17)
497 #define CONF_EW (_ULCAST_(3) << 18)
498 #define CONF_EP (_ULCAST_(15)<< 24)
499 #define CONF_EC (_ULCAST_(7) << 28)
500 #define CONF_CM (_ULCAST_(1) << 31)
503 #define R4K_CONF_SW (_ULCAST_(1) << 20)
504 #define R4K_CONF_SS (_ULCAST_(1) << 21)
505 #define R4K_CONF_SB (_ULCAST_(3) << 22)
508 #define R5K_CONF_SE (_ULCAST_(1) << 12)
509 #define R5K_CONF_SS (_ULCAST_(3) << 20)
512 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
513 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
514 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
515 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
516 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
517 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
520 #define R10K_CONF_DN (_ULCAST_(3) << 3)
521 #define R10K_CONF_CT (_ULCAST_(1) << 5)
522 #define R10K_CONF_PE (_ULCAST_(1) << 6)
523 #define R10K_CONF_PM (_ULCAST_(3) << 7)
524 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
525 #define R10K_CONF_SB (_ULCAST_(1) << 13)
526 #define R10K_CONF_SK (_ULCAST_(1) << 14)
527 #define R10K_CONF_SS (_ULCAST_(7) << 16)
528 #define R10K_CONF_SC (_ULCAST_(7) << 19)
529 #define R10K_CONF_DC (_ULCAST_(7) << 26)
530 #define R10K_CONF_IC (_ULCAST_(7) << 29)
533 #define VR41_CONF_CS (_ULCAST_(1) << 12)
534 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
535 #define VR41_CONF_BP (_ULCAST_(1) << 16)
536 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
537 #define VR41_CONF_AD (_ULCAST_(1) << 23)
540 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
541 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
542 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
543 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
544 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
545 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
546 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
547 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
548 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
551 #define TX49_CONF_DC (_ULCAST_(1) << 16)
552 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
553 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
554 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
557 #define MIPS_CONF_VI (_ULCAST_(1) << 3)
558 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
559 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
560 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
561 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
562 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
563 #define MIPS_CONF_BE (_ULCAST_(1) << 15)
564 #define MIPS_CONF_BM (_ULCAST_(1) << 16)
565 #define MIPS_CONF_MM (_ULCAST_(3) << 17)
566 #define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
567 #define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
568 #define MIPS_CONF_SB (_ULCAST_(1) << 21)
569 #define MIPS_CONF_UDI (_ULCAST_(1) << 22)
570 #define MIPS_CONF_DSP (_ULCAST_(1) << 23)
571 #define MIPS_CONF_ISP (_ULCAST_(1) << 24)
572 #define MIPS_CONF_KU (_ULCAST_(3) << 25)
573 #define MIPS_CONF_K23 (_ULCAST_(3) << 28)
574 #define MIPS_CONF_M (_ULCAST_(1) << 31)
579 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
580 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
581 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
582 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
583 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
584 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
585 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
588 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
591 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
594 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
597 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
600 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
603 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
606 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
608 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
609 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
610 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
611 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
612 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
613 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
614 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
615 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
617 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
618 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
619 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
620 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
621 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
622 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
623 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
624 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
625 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
626 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
627 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
628 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
629 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
630 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
631 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
632 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
633 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
634 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
635 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
636 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
637 #define MIPS_CONF3_PW (_ULCAST_(1) << 24)
638 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
639 #define MIPS_CONF3_BI (_ULCAST_(1) << 26)
640 #define MIPS_CONF3_BP (_ULCAST_(1) << 27)
641 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
642 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
643 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
646 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
648 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
650 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
653 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
655 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
656 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
657 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
658 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
659 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
661 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
663 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
664 #define MIPS_CONF4_AE (_ULCAST_(1) << 28)
665 #define MIPS_CONF4_IE (_ULCAST_(3) << 29)
666 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
668 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
669 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
670 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
671 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
672 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
673 #define MIPS_CONF5_VP (_ULCAST_(1) << 7)
674 #define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
675 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
676 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
677 #define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
678 #define MIPS_CONF5_MI (_ULCAST_(1) << 17)
679 #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
680 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
681 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
682 #define MIPS_CONF5_CV (_ULCAST_(1) << 29)
683 #define MIPS_CONF5_K (_ULCAST_(1) << 30)
688 #define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
690 #define MTI_CONF6_R6 (_ULCAST_(1) << 2)
692 #define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
693 #define MTI_CONF6_SYND (_ULCAST_(1) << 13)
695 #define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
697 #define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
699 #define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
706 #define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
708 #define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
710 #define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
712 #define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
714 #define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
716 #define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
718 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
720 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
722 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
723 #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
729 #define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
734 #define MTI_CONF7_PTC (_ULCAST_(1) << 19)
737 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
740 #define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
741 #define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
742 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
743 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
744 #define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
745 #define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
746 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
747 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
748 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
749 #define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
750 #define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
751 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
752 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
755 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
756 #define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
757 #define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
758 #define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
759 #define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
761 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
762 #define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
763 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
764 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
765 #define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
766 #define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
767 #define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
768 #define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
769 #define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
773 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
775 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
776 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
777 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
778 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
779 #define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
782 #define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
785 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
791 #define MIPS_MAAR_S (_ULCAST_(1) << 1)
792 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
798 #define MIPS_MAARX_VH (_ULCAST_(1) << 31)
803 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
807 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
809 #define MIPS_EBASE_WG (_ULCAST_(1) << 11)
811 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
815 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
819 #define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
825 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
827 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
829 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
831 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
833 #define MIPS_SEGCFG_UUSK _ULCAST_(7)
834 #define MIPS_SEGCFG_USK _ULCAST_(5)
835 #define MIPS_SEGCFG_MUSUK _ULCAST_(4)
836 #define MIPS_SEGCFG_MUSK _ULCAST_(3)
837 #define MIPS_SEGCFG_MSK _ULCAST_(2)
838 #define MIPS_SEGCFG_MK _ULCAST_(1)
839 #define MIPS_SEGCFG_UK _ULCAST_(0)
882 #define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
884 #define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
886 #define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
888 #define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
890 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
892 #define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
894 #define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
896 #define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
898 #define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
900 #define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
902 #define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
904 #define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
906 #define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
908 #define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
910 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
912 #define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
914 #define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
931 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
933 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
935 #define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
937 #define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
939 #define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
941 #define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
943 #define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
957 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
960 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
963 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
970 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
971 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
972 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
986 #define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
987 #define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
988 #define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
989 #define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
990 #define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
991 #define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
992 #define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
1031 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1033 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1035 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1038 #define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1040 #define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1042 #define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1044 #define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1046 #define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1048 #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1075 #define MIPS_DEBUG_DBP (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1092 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
1093 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
1094 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1095 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1096 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
1097 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
1098 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1099 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1100 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1101 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1107 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1109 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1111 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1113 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1115 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1117 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1119 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1121 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1123 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1129 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1135 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1138 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1141 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1143 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1145 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1147 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1149 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1151 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1153 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1155 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1163 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1165 #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1166 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1167 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
2767 if ((res & _ULCAST_(1))) in tlb_read()