Lines Matching refs:ALCHEMY_GPIO1_BASE
17 #define ALCHEMY_GPIO1_BASE 0 macro
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
47 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1000_gpio1_to_irq()
58 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0; in au1000_irq_to_gpio()
65 gpio -= ALCHEMY_GPIO1_BASE; in au1500_gpio1_to_irq()
95 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0; in au1500_irq_to_gpio()
111 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1100_gpio1_to_irq()
128 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0; in au1100_irq_to_gpio()
138 gpio -= ALCHEMY_GPIO1_BASE; in au1550_gpio1_to_irq()
167 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0; in au1550_irq_to_gpio()
172 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16; in au1550_irq_to_gpio()
182 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); in au1200_gpio1_to_irq()
203 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0; in au1200_irq_to_gpio()
220 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); in alchemy_gpio1_set_value()
227 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); in alchemy_gpio1_get_value()
233 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); in alchemy_gpio1_direction_input()
249 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX)); in alchemy_gpio1_is_valid()