asm/mach-au1x00/au1000.h

6  * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
48 #define ALCHEMY_GPIC_INT_LAST	(ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
293 #define MEM_SDADDR_CSBA_N(N)	((N) & (0x03FF << 22) >> 12)
358 #  define SYS_CNTRL_BT1		(1 << 12)
392 #  define SYS_PF_U1		(1 << 12)	/* GPIO21/U1TXD */
445 #define SYS_PINFUNC_U1T		(1 << 12)
537 #define PCI_CONFIG_ET		(1 << 26) /* error in target mode */
544 #define PCI_CONFIG_NC		(1 << 16) /* mark mem access non-coherent */
545 #define PCI_CONFIG_IA		(1 << 15) /* INTA# enabled (target mode) */
547 #define PCI_CONFIG_IS		(1 << 12) /* int on PCI_SERR# */
549 #define PCI_CONFIG_ITM		(1 << 10) /* int on target abort (as master) */
550 #define PCI_CONFIG_ITT		(1 << 9)  /* int on target abort (as target) */
556 #define PCI_CONFIG_ST		(1 << 5)  /* swap data by target transactions */
559 #define PCI_CONFIG_R2H		(1 << 2)  /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H		(1 << 1)  /* REQ1# to hi-prio arbiter */
561 #define PCI_CONFIG_CH		(1 << 0)  /* PCI ctl to hi-prio arbiter */
584 #define PCI_TIMEOUT_TO(x)	((x) & 0xff)	/* target ready timeout */
608 static inline void alchemy_wrsys(unsigned long v, int regofs)  in alchemy_wrsys()  argument
612 	__raw_writel(v, b + regofs);  in alchemy_wrsys()
624 static inline void alchemy_wrsmem(unsigned long v, int regofs)  in alchemy_wrsmem()  argument
628 	__raw_writel(v, b + regofs);  in alchemy_wrsmem()
632 /* Early Au1000 have a write-only SYS_CPUPLL register. */
649 	 * early revisions of Alchemy SOCs.  It disables the bus trans-  in au1xxx_cpu_needs_config_od()
671 #define ALCHEMY_CPU_UNKNOWN	-1
758 		for (i = 10000; i; i--)  in alchemy_uart_putchar()
760 	} while (--timeout);  in alchemy_uart_putchar()
820  * GPIO controller or a on-chip peripheral.
825 	/* wake-from-str pins 0-3 */
828 	/* external clock sources for PSCs: 4-5 */
830 	/* 8bit MMC interface on SD0: 6-9 */
835 	/* UART1 pins: 11-18 */
839 	/* UART0 pins: 19-24 */
842 	/* UART2: 25-26 */
844 	/* UART3: 27-28 */
846 	/* LCD controller PWMs, ext pixclock: 29-31 */
848 	/* SD1 interface: 32-37 */
851 	/* SD2 interface: 38-43 */
854 	/* PSC0/1 clocks: 44-45 */
856 	/* PSCs: 46-49/50-53/54-57/58-61 */
865 	/* PCMCIA interface: 62-70 */
869 	/* camera interface H/V sync inputs: 71-72 */
871 	/* PSC2/3 clocks: 73-74 */
881 /* Au1300 allows to disconnect certain blocks from internal power supply */