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6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
48 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
81 #define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
544 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
559 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
632 /* Early Au1000 have a write-only SYS_CPUPLL register. */
649 * early revisions of Alchemy SOCs. It disables the bus trans- in au1xxx_cpu_needs_config_od()
671 #define ALCHEMY_CPU_UNKNOWN -1
758 for (i = 10000; i; i--) in alchemy_uart_putchar()
760 } while (--timeout); in alchemy_uart_putchar()
820 * GPIO controller or a on-chip peripheral.
825 /* wake-from-str pins 0-3 */
828 /* external clock sources for PSCs: 4-5 */
830 /* 8bit MMC interface on SD0: 6-9 */
835 /* UART1 pins: 11-18 */
839 /* UART0 pins: 19-24 */
842 /* UART2: 25-26 */
844 /* UART3: 27-28 */
846 /* LCD controller PWMs, ext pixclock: 29-31 */
848 /* SD1 interface: 32-37 */
851 /* SD2 interface: 38-43 */
854 /* PSC0/1 clocks: 44-45 */
856 /* PSCs: 46-49/50-53/54-57/58-61 */
865 /* PCMCIA interface: 62-70 */
869 /* camera interface H/V sync inputs: 71-72 */
871 /* PSC2/3 clocks: 73-74 */