76 		struct {		/* only used for ciu/ciu2 */
83 	int ciu_node; /* NUMA node number of the CIU */
804 	 * For non-v2 CIU, we will allow only single CPU affinity.  in octeon_irq_ciu_set_affinity()
937  * Newer octeon chips have support for lockless CIU operation.
940 	.name = "CIU",
952 	.name = "CIU",
965  * Newer octeon chips have support for lockless CIU operation.
968 	.name = "CIU",
980 	.name = "CIU",
993 	.name = "CIU",
1005 	.name = "CIU",
1019 	.name = "CIU-M",
1031 	.name = "CIU-M",
1043 	.name = "CIU-GPIO",
1058 	.name = "CIU-GPIO",
1111 	.name = "CIU-W",
1119 	.name = "CIU-W",
1212 	unsigned int ciu, bit;  in octeon_irq_ciu_xlat()  local
1215 	ciu = intspec[0];  in octeon_irq_ciu_xlat()
1218 	if (ciu >= dd->num_sum || bit > 63)  in octeon_irq_ciu_xlat()
1221 	*out_hwirq = (ciu << 6) | bit;  in octeon_irq_ciu_xlat()
1395 	 * Disable All CIU Interrupts. The ones we need will be  in octeon_irq_init_ciu_percpu()
1433 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu()
1446 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu2()
1583 	/* Enable the CIU lines */  in octeon_irq_init_ciu()
1901 	.name = "CIU-GPIO",
1922 	unsigned int ciu, bit;  in octeon_irq_ciu2_xlat()  local
1924 	ciu = intspec[0];  in octeon_irq_ciu2_xlat()
1927 	*out_hwirq = (ciu << 6) | bit;  in octeon_irq_ciu2_xlat()
2122 	/* Enable the CIU lines */  in octeon_irq_init_ciu2()
2853 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu3()
2908 		/* Only do per CPU things if it is the CIU of the boot node. */  in octeon_irq_init_ciu3()
2929 		/* Only do per CPU things if it is the CIU of the boot node. */  in octeon_irq_init_ciu3()
2935 		/* Enable the CIU lines */  in octeon_irq_init_ciu3()
2944 	{.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},