dts/ralink/mt7621.dtsi

14 		#size-cells = <0>;
16 		cpu@0 {
19 			reg = <0>;
30 		#address-cells = <0>;
56 		reg = <0x1e000000 0x100000>;
57 		ranges = <0x0 0x1e000000 0x0fffff>;
62 		sysc: syscon@0 {
64 			reg = <0x0 0x100>;
75 			reg = <0x100 0x100>;
84 			gpio-ranges = <&pinctrl 0 0 95>;
86 			reg = <0x600 0x100>;
93 			reg = <0x900 0x100>;
101 			#size-cells = <0>;
106 			pinctrl-0 = <&i2c_pins>;
111 			reg = <0x5000 0x1000>;
116 			reg = <0xc00 0x100>;
132 			reg = <0xb00 0x100>;
141 			#size-cells = <0>;
144 			pinctrl-0 = <&spi_pins>;
238 		reg = <0x1e130000 0x4000>;
249 		pinctrl-0 = <&sdhci_pins>;
262 		reg = <0x1e1c0000 0x1000
263 		       0x1e1d0700 0x0100>;
275 		reg = <0x1fbc0000 0x2000>;
291 		reg = <0x1fbf0000 0x8000>;
296 		reg = <0x1fbf8000 0x8000>;
301 		reg = <0x1e100000 0x10000>;
308 		#size-cells = <0>;
319 		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
321 		gmac0: mac@0 {
323 			reg = <0>;
347 			#size-cells = <0>;
351 				reg = <0x1f>;
361 					#size-cells = <0>;
363 					port@0 {
365 						reg = <0>;
423 		reg = <0x1e140000 0x100>, /* host-pci bridge registers */
424 		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */
425 		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */
426 		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */
431 		pinctrl-0 = <&pcie_pins>;
435 		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
436 			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
439 		interrupt-map-mask = <0xF800 0 0 0>;
440 		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
441 				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
442 				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
448 		pcie@0,0 {
449 			reg = <0x0000 0 0 0 0>;
454 			interrupt-map-mask = <0 0 0 0>;
455 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
463 		pcie@1,0 {
464 			reg = <0x0800 0 0 0 0>;
469 			interrupt-map-mask = <0 0 0 0>;
470 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
478 		pcie@2,0 {
479 			reg = <0x1000 0 0 0 0>;
484 			interrupt-map-mask = <0 0 0 0>;
485 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
488 			phys = <&pcie2_phy 0>;
496 		reg = <0x1e149000 0x0700>;
503 		reg = <0x1e14a000 0x0700>;