122 #define PVR_IS_FULL(_pvr)	(_pvr.pvr[0] & PVR0_PVR_FULL_MASK)  argument
123 #define PVR_USE_BARREL(_pvr)	(_pvr.pvr[0] & PVR0_USE_BARREL_MASK)  argument
124 #define PVR_USE_DIV(_pvr)	(_pvr.pvr[0] & PVR0_USE_DIV_MASK)  argument
125 #define PVR_USE_HW_MUL(_pvr)	(_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)  argument
126 #define PVR_USE_FPU(_pvr)	(_pvr.pvr[0] & PVR0_USE_FPU_MASK)  argument
127 #define PVR_USE_FPU2(_pvr)	(_pvr.pvr[2] & PVR2_USE_FPU2_MASK)  argument
128 #define PVR_USE_ICACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)  argument
129 #define PVR_USE_DCACHE(_pvr)	(_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)  argument
130 #define PVR_VERSION(_pvr)	((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)  argument
131 #define PVR_USER1(_pvr)		(_pvr.pvr[0] & PVR0_USER1_MASK)  argument
132 #define PVR_USER2(_pvr)		(_pvr.pvr[1] & PVR1_USER2_MASK)  argument
134 #define PVR_D_OPB(_pvr)		(_pvr.pvr[2] & PVR2_D_OPB_MASK)  argument
135 #define PVR_D_LMB(_pvr)		(_pvr.pvr[2] & PVR2_D_LMB_MASK)  argument
136 #define PVR_I_OPB(_pvr)		(_pvr.pvr[2] & PVR2_I_OPB_MASK)  argument
137 #define PVR_I_LMB(_pvr)		(_pvr.pvr[2] & PVR2_I_LMB_MASK)  argument
138 #define PVR_INTERRUPT_IS_EDGE(_pvr) \  argument
139 			(_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
140 #define PVR_EDGE_IS_POSITIVE(_pvr) \  argument
141 			(_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
142 #define PVR_USE_MSR_INSTR(_pvr)		(_pvr.pvr[2] & PVR2_USE_MSR_INSTR)  argument
143 #define PVR_USE_PCMP_INSTR(_pvr)	(_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)  argument
144 #define PVR_AREA_OPTIMISED(_pvr)	(_pvr.pvr[2] & PVR2_AREA_OPTIMISED)  argument
145 #define PVR_USE_MUL64(_pvr)		(_pvr.pvr[2] & PVR2_USE_MUL64_MASK)  argument
146 #define PVR_OPCODE_0x0_ILLEGAL(_pvr) \  argument
147 			(_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
148 #define PVR_UNALIGNED_EXCEPTION(_pvr) \  argument
149 			(_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
150 #define PVR_ILL_OPCODE_EXCEPTION(_pvr) \  argument
151 			(_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
152 #define PVR_IOPB_BUS_EXCEPTION(_pvr) \  argument
153 			(_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
154 #define PVR_DOPB_BUS_EXCEPTION(_pvr) \  argument
155 			(_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
156 #define PVR_DIV_ZERO_EXCEPTION(_pvr) \  argument
157 			(_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
158 #define PVR_FPU_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_FPU_EXC_MASK)  argument
159 #define PVR_FSL_EXCEPTION(_pvr)		(_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)  argument
161 #define PVR_DEBUG_ENABLED(_pvr)		(_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)  argument
162 #define PVR_NUMBER_OF_PC_BRK(_pvr) \  argument
163 			((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
164 #define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \  argument
165 			((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
166 #define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \  argument
167 			((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
168 #define PVR_FSL_LINKS(_pvr)	((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)  argument
170 #define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \  argument
171 		((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
172 #define PVR_ICACHE_USE_FSL(_pvr) \  argument
173 		(_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
174 #define PVR_ICACHE_ALLOW_WR(_pvr) \  argument
175 		(_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
176 #define PVR_ICACHE_LINE_LEN(_pvr) \  argument
177 		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
178 #define PVR_ICACHE_BYTE_SIZE(_pvr) \  argument
179 		(1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
181 #define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \  argument
182 			((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
183 #define PVR_DCACHE_USE_FSL(_pvr)	(_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)  argument
184 #define PVR_DCACHE_ALLOW_WR(_pvr) \  argument
185 			(_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
187 #define PVR_DCACHE_LINE_LEN(_pvr) \  argument
188 		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
189 #define PVR_DCACHE_BYTE_SIZE(_pvr) \  argument
190 		(1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
192 #define PVR_DCACHE_USE_WRITEBACK(_pvr) \  argument
193 			((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
195 #define PVR_ICACHE_BASEADDR(_pvr) \  argument
196 			(_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
197 #define PVR_ICACHE_HIGHADDR(_pvr) \  argument
198 			(_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
199 #define PVR_DCACHE_BASEADDR(_pvr) \  argument
200 			(_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
201 #define PVR_DCACHE_HIGHADDR(_pvr) \  argument
202 			(_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
204 #define PVR_TARGET_FAMILY(_pvr) \  argument
205 			((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
207 #define PVR_MSR_RESET_VALUE(_pvr) \  argument
208 			(_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
211 #define PVR_USE_MMU(_pvr)		((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)  argument
212 #define PVR_MMU_ITLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)  argument
213 #define PVR_MMU_DTLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)  argument
214 #define PVR_MMU_TLB_ACCESS(_pvr)	(_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)  argument
215 #define PVR_MMU_ZONES(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ZONES)  argument
219 #define PVR_ENDIAN(_pvr)	(_pvr.pvr[0] & PVR0_ENDI)  argument