ifpsp060/src/fpsp.S

9449 # answer is inexact, so set INEX2 and AINEX in the user's FPSR.
10126 #	- Set FPSR exception status dz bit, ccode inf bit, and		#
10149 #	- set FPSR exception status operr bit, condition code	#
11626 	fmov.l		&0x0,%fpsr		# clear FPSR
11666 	fmov.l		&0x0,%fpsr		# clear FPSR
12276 # now, round to extended(and don't alter the FPSR).
12297 	fmov.l		&0x0,%fpsr		# clear FPSR
13056 # now, round to extended(and don't alter the FPSR).
13077 	fmov.l		&0x0,%fpsr		# clear FPSR
13326 # then store the resulting FPSR bits.					#
13330 #	For zeroes/infs/NANs, return the same while setting the FPSR	#
13344 	fmov.l		&0x0,%fpsr		# clear FPSR
13348 	fmov.l		%fpsr,%d0		# save FPSR
13551 	fmov.l		&0x0,%fpsr		# clear FPSR
13556 	fmov.l		%fpsr,%d1		# save FPSR
13638 	fmov.l		&0x0,%fpsr		# clear FPSR
13644 	fmov.l		%fpsr,%d1		# save FPSR
13772 	fmov.l		%fpsr,%d0		# save FPSR
13997 	fmov.l		&0x0,%fpsr		# clear FPSR
14024 	fmov.l		&0x0,%fpsr		# clear FPSR
14073 	fmov.l		&0x0,%fpsr		# clear FPSR
14344 	fmov.l		&0x0,%fpsr		# clear FPSR
14348 	fmov.l		%fpsr,%d1		# save FPSR
14371 	fmov.l		&0x0,%fpsr		# set FPSR
14428 	fmov.l		&0x0,%fpsr		# clear FPSR
14458 	fmov.l		&0x0,%fpsr		# clear FPSR
14486 	fmov.l		&0x0,%fpsr		# clear FPSR
14513 	fmov.l		&0x0,%fpsr		# clear FPSR
14631 # the correct result exponent and return. Set FPSR bits as appropriate.	#
14666 	fmov.l		&0x0,%fpsr		# clear FPSR
14778 	fmov.l		&0x0,%fpsr		# clear FPSR
14812 	fmov.l		&0x0,%fpsr		# clear FPSR
14874 	fmov.l		&0x0,%fpsr		# clear FPSR
15084 # the correct result exponent and return. Set FPSR bits as appropriate.	#
15119 	fmov.l		&0x0,%fpsr		# clear FPSR
15231 	fmov.l		&0x0,%fpsr		# clear FPSR
15265 	fmov.l		&0x0,%fpsr		# clear FPSR
15327 	fmov.l		&0x0,%fpsr		# clear FPSR
15670 	fmov.l		&0x0,%fpsr		# clear FPSR
15720 	fmov.l		&0x0,%fpsr		# clear FPSR
15726 	fmov.l		%fpsr,%d1		# save FPSR
16162 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap	#
16168 #	Make sure the appropriate FPSR bits are set before exiting.	#
16267 # to see whether the condition (specified by the stacked FPSR) is true	#
16270 # bits are set in the stacked FPSR. If the BSUN exception is enabled,	#
16287 	fmov.l		%d1,%fpsr		# insert into FPSR
16339 # (This is assuming the mutual exclusiveness of FPSR cc bit groupings	#