Lines Matching refs:d0
31 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
45 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
46 btst #0,%d0 /* check if region enabled */
48 andl #0xfffc0000,%d0
50 addl #0x00040000,%d0 /* convert mask to size */
58 addl %d1,%d0 /* total mem size in d0 */
64 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
65 andil #0xfffff000,%d0 /* mask out chip select options */
66 negl %d0 /* negate bits */
71 clrl %d0
76 moveql #1, %d0
77 lsll %d2, %d0 /* 2 ^ exponent */
85 addl %d1, %d0 /* Total size of SDRAM in d0 */
156 movel #CACHE_INIT,%d0 /* disable cache */
157 movec %d0,%CACR
163 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
164 movec %d0,%MBAR /* set it */
186 addl %a7,%d0
187 movel %d0,_ramend /* set end ram addr */
196 movel #ACR0_MODE,%d0 /* set RAM region for caching */
197 movec %d0,%ACR0
198 movel #ACR1_MODE,%d0 /* anything else to cache? */
199 movec %d0,%ACR1
201 movel #ACR2_MODE,%d0
202 movec %d0,%ACR2
203 movel #ACR3_MODE,%d0
204 movec %d0,%ACR3
206 movel #CACHE_MODE,%d0 /* enable cache */
207 movec %d0,%CACR
214 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
215 movec %d0,%MMUBAR
216 movel #MMUOR_CA,%d0 /* clear TLB entries */
217 movel %d0,MMUOR
218 movel #0,%d0 /* set ASID to 0 */
219 movec %d0,%asid
221 movel #MMUCR_EN,%d0 /* Enable the identity map */
222 movel %d0,MMUCR
238 movel 8(%a0),%d0 /* get size of ROMFS */
239 addql #8,%d0 /* allow for rounding */
240 andl #0xfffffffc, %d0 /* whole words */
242 addl %d0,%a0 /* copy from end */
243 addl %d0,%a1 /* copy from end */
247 movel -(%a0),%d0 /* copy dword */
248 movel %d0,-(%a1)
263 clrl %d0 /* set value */
265 movel %d0,(%a0)+ /* clear each word */
280 movel #CPU_COLDFIRE,%d0
281 movel %d0,m68k_cputype /* Mark us as a ColdFire */
282 movel #MMU_COLDFIRE,%d0
283 movel %d0,m68k_mmutype
284 movel #FPUTYPE,%d0
285 movel %d0,m68k_fputype /* Mark FPU type */
286 movel #MACHINE,%d0
287 movel %d0,m68k_machtype /* Mark machine type */