Lines Matching refs:_ULCAST_
184 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
187 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
190 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
192 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
194 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
196 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
199 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
207 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
209 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
212 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
216 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
218 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
220 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
222 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
229 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
232 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
237 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
240 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
243 #define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
256 #define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT)
259 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
262 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
272 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
274 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
276 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
279 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
281 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
284 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
287 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
289 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
291 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
295 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
297 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
299 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
302 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
304 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
307 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
310 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
312 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
314 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
319 #define CSR_GTLBC_RID (_ULCAST_(0xff) << CSR_GTLBC_RID_SHIFT)
321 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
323 #define CSR_GTLBC_USERID (_ULCAST_(0x1) << CSR_GTLBC_USERID_SHIFT)
326 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
331 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
338 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
341 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
352 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
355 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
358 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
361 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
364 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
367 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
370 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
375 #define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT)
378 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
381 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
384 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
387 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
391 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f))
395 #define CSR_RVACFG_RDVA (_ULCAST_(0xf))
400 #define CSR_CPUID_COREID _ULCAST_(0x1ff)
405 #define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT)
408 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
410 #define CSR_CONF1_KSNUM _ULCAST_(0xf)
418 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
421 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
424 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
427 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
461 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
463 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
464 #define CSR_TCFG_EN (_ULCAST_(0x1))
478 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
481 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
483 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
485 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
490 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
493 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
494 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
495 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
496 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
498 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
499 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
500 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
501 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
503 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
505 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
507 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
509 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
511 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
513 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
515 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
517 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
519 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
521 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
524 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
525 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
526 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
527 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
532 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
535 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
538 #define CSR_GINTC_VIP (_ULCAST_(0xff))
545 #define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT)
547 #define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT)
549 #define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT)
555 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
557 #define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT)
559 #define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT)
561 #define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT)
563 #define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT)
565 #define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT)
567 #define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT)
569 #define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT)
571 #define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT)
573 #define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT)
575 #define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT)
577 #define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT)
579 #define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT)
581 #define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT)
583 #define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT)
585 #define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT)
588 #define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT)
590 #define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT)
592 #define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT)
596 #define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT)
598 #define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT)
600 #define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT)
602 #define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT)
604 #define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT)
617 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
637 #define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT)
639 #define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT)
641 #define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT)
643 #define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT)
645 #define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT)
647 #define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT)
650 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
654 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
657 #define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT)
659 #define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT)
661 #define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT)
664 #define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT)
671 #define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT)
674 #define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT)
676 #define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT)
678 #define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT)
680 #define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT)
682 #define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT)
684 #define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT)
686 #define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT)
688 #define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT)
690 #define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT)
692 #define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT)
694 #define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT)
696 #define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT)
698 #define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT)
700 #define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT)
703 #define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT)
705 #define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT)
708 #define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT)
710 #define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT)
712 #define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT)
714 #define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT)
716 #define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT)
718 #define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT)
721 #define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT)
723 #define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT)
725 #define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT)
727 #define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT)
732 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
735 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
737 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff))
742 #define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT)
745 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
749 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
752 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
754 #define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT)
759 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
762 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
765 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
767 #define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT)
769 #define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT)
771 #define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT)
773 #define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT)
775 #define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT)
777 #define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT)
779 #define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT)
781 #define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT)
783 #define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT)
785 #define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT)
787 #define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT)
789 #define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT)
791 #define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT)
793 #define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT)
795 #define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT)
797 #define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT)
799 #define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT)
804 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
807 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
810 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
813 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
816 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
819 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
824 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
827 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
830 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
834 #define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT)
836 #define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT)
838 #define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT)
840 #define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT)
880 #define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16)
881 #define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17)
882 #define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18)
883 #define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19)
884 #define CSR_PERFCTRL_IE (_ULCAST_(1) << 20)
979 #define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT)
986 #define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0)
988 #define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1)
990 #define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0)
992 #define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1)
994 #define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2)
996 #define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3)
998 #define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4)
1000 #define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5)
1002 #define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6)
1004 #define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7)
1006 #define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC)
1008 #define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER)
1010 #define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI)
1011 #define ECFGF(hwirq) (_ULCAST_(1) << hwirq)
1074 #define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63)
1075 #define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62)
1076 #define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61)
1078 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48)
1254 #define ENTRYLO_V (_ULCAST_(1) << 0)
1255 #define ENTRYLO_D (_ULCAST_(1) << 1)
1257 #define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT)
1259 #define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT)
1260 #define ENTRYLO_G (_ULCAST_(1) << 6)
1261 #define ENTRYLO_NR (_ULCAST_(1) << 61)
1262 #define ENTRYLO_NX (_ULCAST_(1) << 62)
1415 #define FPU_CSR_TM (_ULCAST_(1) << FPU_CSR_TM_SHIFT)