Lines Matching +full:0 +full:x700

11  * Bit4: ordering or completion (0: completion, 1: ordering)
12  * Bit3: barrier for previous read (0: true, 1: false)
13  * Bit2: barrier for previous write (0: true, 1: false)
14  * Bit1: barrier for succeeding read (0: true, 1: false)
15  * Bit0: barrier for succeeding write (0: true, 1: false)
17  * Hint 0x700: barrier for "read after read" from the same address
20 #define DBAR(hint) __asm__ __volatile__("dbar %0 " : : "I"(hint) : "memory")
22 #define crwrw		0b00000
23 #define cr_r_		0b00101
24 #define c_w_w		0b01010
26 #define orwrw		0b10000
27 #define or_r_		0b10101
28 #define o_w_w		0b11010
30 #define orw_w		0b10010
31 #define or_rw		0b10100
55 #define __WEAK_LLSC_MB		"	dbar 0x700	\n"
64  * array_index_mask_nospec() - generate a ~0 mask when index < size, 0 otherwise
69  *     0 - (@index < @size)
78 		"sltu	%0, %1, %2\n\t"  in array_index_mask_nospec()
80 		"sub.w	%0, $zero, %0\n\t"  in array_index_mask_nospec()
82 		"sub.d	%0, $zero, %0\n\t"  in array_index_mask_nospec()
104 } while (0)
135 } while (0)