36 # define DPRINT(a...)	do { printk("%s %u: ", __func__, __LINE__); printk (a); } while (0)  macro
51 # define DPRINT(a...)  macro
322 		DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);  in set_rse_reg()
329 	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",  in set_rse_reg()
350 		DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);  in set_rse_reg()
359 	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);  in set_rse_reg()
366 	DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",  in set_rse_reg()
376 	DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);  in set_rse_reg()
395 		DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);  in get_rse_reg()
402 	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",  in get_rse_reg()
421 		DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);  in get_rse_reg()
430 	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);  in get_rse_reg()
438 		DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats);  in get_rse_reg()
484 	DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n",  in setreg()
499 	DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);  in setreg()
505 	DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);  in setreg()
549 		DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum));  in setfpreg()
617 			DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n",  in getfpreg()
659 	DPRINT("addr_base=%lx offset=0x%x\n", addr,  GR_OFFS(regnum));  in getreg()
717 		DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa);  in emulate_load_updates()
748 		DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2);  in emulate_load_updates()
789 		DPRINT("unknown size: x6=%d\n", ld.x6_sz);  in emulate_load_int()
913 	DPRINT("st%d [%lx]=%lx\n", len, ifa, r2);  in emulate_store_int()
916 		DPRINT("unknown size: x6=%d\n", ld.x6_sz);  in emulate_store_int()
947 		DPRINT("imm=%lx r3=%lx\n", imm, ifa);  in emulate_store_int()
1074 		DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);  in emulate_load_floatpair()
1176 		DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);  in emulate_load_float()
1262 	DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);  in emulate_store_float()
1293 		DPRINT("imm=%lx r3=%lx\n", imm, ifa);  in emulate_store_float()
1392 	DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n",  in ia64_handle_unaligned()
1409 	DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "  in ia64_handle_unaligned()
1467 		DPRINT("forcing PSR_ED\n");  in ia64_handle_unaligned()
1528 	DPRINT("ret=%d\n", ret);  in ia64_handle_unaligned()
1541 	DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip);  in ia64_handle_unaligned()