Lines Matching refs:r18
115 movl r18=PAGE_SHIFT
129 cmp.ne p8,p0=r18,r26
130 sub r27=r26,r18
132 (p8) dep r25=r18,r25,2,6
137 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
148 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
149 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
154 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
163 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
167 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
169 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
178 (p7) ld8 r18=[r21] // read *pte
181 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
187 ITC_I_AND_D(p10, p11, r18, r24) // insert the instruction TLB entry and
239 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
266 1: ld8 r18=[r17] // read *pte
269 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
272 ITC_I(p0, r18, r19)
284 cmp.ne p7,p0=r18,r19
310 1: ld8 r18=[r17] // read *pte
313 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
316 ITC_D(p0, r18, r19)
328 cmp.ne p7,p0=r18,r19
360 shr.u r18=r16,57 // move address bit 61 to bit 4
362 andcm r18=0x10,r18 // bit 4=~address-bit(61)
366 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
369 ITC_I(p0, r19, r18) // insert the TLB entry
424 ITC_D(p7, r19, r18) // insert the TLB entry
458 MOV_FROM_ITIR(r18)
461 extr.u r18=r18,2,6 // get the faulting page size
464 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
465 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
468 shr.u r18=r16,r18
478 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
479 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
482 shr.u r18=r22,PUD_SHIFT // shift pud index into position
484 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
490 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
494 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
497 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
543 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
549 1: ld8 r18=[r17]
551 mov ar.ccv=r18 // set compare value for cmpxchg
552 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
553 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
558 (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present
560 ITC_D(p6, r25, r18) // install updated PTE
568 ld8 r18=[r17] // read PTE again
570 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
577 1: ld8 r18=[r17]
579 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
582 st8 [r17]=r18 // store back updated PTE
583 ITC_D(p0, r18, r16) // install updated PTE
604 MOV_FROM_IIP(r18)
607 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
610 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
615 1: ld8 r18=[r17]
617 mov ar.ccv=r18 // set compare value for cmpxchg
618 or r25=_PAGE_A,r18 // set the accessed bit
619 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
624 (p6) cmp.eq p6,p7=r26,r18 // Only if page present
634 ld8 r18=[r17] // read PTE again
636 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
643 1: ld8 r18=[r17]
645 or r18=_PAGE_A,r18 // set the accessed bit
648 st8 [r17]=r18 // store back updated PTE
649 ITC_I(p0, r18, r16) // install updated PTE
664 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
670 1: ld8 r18=[r17]
672 mov ar.ccv=r18 // set compare value for cmpxchg
673 or r25=_PAGE_A,r18 // set the dirty bit
674 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
679 (p6) cmp.eq p6,p7=r26,r18 // Only if page is present
688 ld8 r18=[r17] // read PTE again
690 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
696 1: ld8 r18=[r17]
698 or r18=_PAGE_A,r18 // set the accessed bit
700 st8 [r17]=r18 // store back updated PTE
701 ITC_D(p0, r18, r16) // install updated PTE
734 mov r18=__IA64_BREAK_SYSCALL // A
752 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
807 MOV_FROM_ITC(p0, p14, r30, r18) // M get cycle for accounting
814 mov r18=ar.bsp // M2 (12 cyc)
828 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // M get last stamp
833 sub r22=r19,r18 // A stime before leave
836 sub r18=r30,r19 // A elapsed time in user
839 add r21=r21,r18 // A sum utime
956 (pKStk) mov r18=r0 // make sure r18 isn't NaT
978 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
992 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
998 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1061 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // time at last check in kernel
1066 sub r22=r19,r18 // stime before leave kernel
1069 sub r18=r20,r19 // elapsed time in user mode
1072 add r21=r21,r18 // sum utime
1200 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1203 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1207 MOV_TO_IPSR(p0, r16, r18)
1232 MOV_FROM_IIM(r18)
1235 shl r18=r18,43 // put sign bit in position (43=64-21)
1239 shr r18=r18,39 // sign extend (39=43-4)
1242 add r17=r17,r18 // now add the offset