Lines Matching +full:ia32 +full:- +full:3 +full:a
1 /* SPDX-License-Identifier: GPL-2.0 */
8 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
9 * chapter 11 IA-64 Processor Abstraction Layer
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
21 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
30 * Note that some of these calls use a static-register only calling
36 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
66 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
83 #define PAL_TEST_PROC 258 /* perform late processor self-test */
87 #define PAL_GET_PSTATE 262 /* get the current P-state */
88 #define PAL_SET_PSTATE 263 /* set the P-state */
94 #define PAL_GET_PSTATE_TYPE_INSTANT 3
113 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
114 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
115 #define PAL_STATUS_ERROR (-3) /* Error */
116 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
121 #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
130 /* Processor cache type at a particular level in the hierarchy */
135 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
149 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
158 at : 2, /* 2-1 Cache mem attr*/
159 reserved : 5, /* 7-3 Reserved */
160 associativity : 8, /* 16-8 Associativity*/
161 line_size : 8, /* 23-17 Line size */
162 stride : 8, /* 31-24 Stride */
163 store_latency : 8, /*39-32 Store latency*/
164 load_latency : 8, /* 47-40 Load latency*/
165 store_hints : 8, /* 55-48 Store hints*/
166 load_hints : 8; /* 63-56 Load hints */
176 u32 alias_boundary : 8, /* 39-32 aliased addr
180 tag_ls_bit : 8, /* 47-40 LSb of addr*/
181 tag_ms_bit : 8, /* 55-48 MSb of addr*/
182 reserved : 8; /* 63-56 Reserved */
224 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
225 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
235 tagprot_lsb : 6, /* Least -do- */
263 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
279 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
286 u64 cache_type : 8, /* 7-0 cache type */
287 level : 8, /* 15-8 level of the
291 way : 8, /* 23-16 way in the set
293 part : 8, /* 31-24 part of the
296 reserved : 32; /* 63-32 is reserved*/
299 u64 cache_type : 8, /* 7-0 cache type */
300 level : 8, /* 15-8 level of the
304 way : 8, /* 23-16 way in the set
306 part : 8, /* 31-24 part of the
309 mesi : 8, /* 39-32 cache line
312 start : 8, /* 47-40 lsb of data to
315 length : 8, /* 55-48 #bits to
318 trigger : 8; /* 63-56 Trigger error
319 * by doing a load
344 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
352 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
373 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
391 * a rendezvous.
414 hd : 1, /* Non-essential hw
435 pm : 1, /* Precise min-state save area */
477 se : 1, /* Shared error. MCA in a
504 mesi : 3, /* Cache line state */
518 is : 1, /* instruction set (1 == ia32) */
555 is : 1, /* instruction set (1 == ia32) */
579 * during cache-cache
591 is : 1, /* instruction set (1 == ia32) */
621 is : 1, /* instruction set (1 == ia32) */
626 reserved3 : 3,
634 level : 3, /* Level of failure */
651 is : 1, /* instruction set (1 == ia32) */
750 * architectural state save area. The other 3 KB is scratch space
756 u64 pmsa_gr[15]; /* GR1 - GR15 */
757 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
758 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
775 * A zero status value indicates call completed without error.
776 * A negative status value indicates reason of call failure.
777 * A positive status value indicates success but an
890 features_avail->pal_bus_features_val = iprv.v0; in ia64_pal_bus_get_features()
892 features_status->pal_bus_features_val = iprv.v1; in ia64_pal_bus_get_features()
894 features_control->pal_bus_features_val = iprv.v2; in ia64_pal_bus_get_features()
916 conf->pcci_status = iprv.status; in ia64_pal_cache_config_info()
917 conf->pcci_info_1.pcci1_data = iprv.v0; in ia64_pal_cache_config_info()
918 conf->pcci_info_2.pcci2_data = iprv.v1; in ia64_pal_cache_config_info()
919 conf->pcci_reserved = iprv.v2; in ia64_pal_cache_config_info()
934 prot->pcpi_status = iprv.status; in ia64_pal_cache_prot_info()
935 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; in ia64_pal_cache_prot_info()
936 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; in ia64_pal_cache_prot_info()
937 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; in ia64_pal_cache_prot_info()
938 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; in ia64_pal_cache_prot_info()
939 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff; in ia64_pal_cache_prot_info()
940 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32; in ia64_pal_cache_prot_info()
970 /* Initialize the tags and data of a data or unified cache line of
983 /* Read the data and tag of a processor controlled cache line for diags */
1006 /* Write the data and tag of a processor-controlled cache line for diags */
1057 /* Switch from IA64-system environment to IA-32 system environment */
1158 /* Get the current P-state information */
1168 /* Set the P-state */
1211 /* Ensure that all outstanding transactions in a processor are completed or that any
1277 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1314 /* Register a platform dependent location with PAL to which it can save
1315 * minimal processor state in the event of a machine check or initialization
1351 * self-test and the required alignment of memory.
1385 pm_info->ppmi_data = iprv.v0; in ia64_pal_perf_mon_info()
1437 * Put everything in a struct so we avoid the global offset table whenever
1455 return -1; in ia64_get_ptce()
1459 ptce->base = iprv.v0; in ia64_get_ptce()
1460 ptce->count[0] = iprv.v1 >> 32; in ia64_get_ptce()
1461 ptce->count[1] = iprv.v1 & 0xffffffff; in ia64_get_ptce()
1462 ptce->stride[0] = iprv.v2 >> 32; in ia64_get_ptce()
1463 ptce->stride[1] = iprv.v2 & 0xffffffff; in ia64_get_ptce()
1501 hints->ph_data = iprv.v1; in ia64_pal_rse_info()
1518 * This is usually called in IA-32 mode.
1528 /* Perform the second phase of processor self-test. */
1565 pal_min_version->pal_version_val = iprv.v0; in ia64_pal_version()
1568 pal_cur_version->pal_version_val = iprv.v1; in ia64_pal_version()
1603 tc_info->pti_val = iprv.v0; in ia64_pal_vm_info()
1659 vm_info_1->pvi1_val = iprv.v0; in ia64_pal_vm_summary()
1661 vm_info_2->pvi2_val = iprv.v1; in ia64_pal_vm_summary()
1699 /* Read a translation register */
1706 tr_valid->piv_val = iprv.v0; in ia64_pal_tr_read()
1721 #define PAL_VISIBILITY_INVAL_ARG -2
1722 #define PAL_VISIBILITY_ERROR -3
1791 mapping->overview.overview_data = iprv.v0; in ia64_pal_logical_to_phys()
1792 mapping->ppli1.ppli1_data = iprv.v1; in ia64_pal_logical_to_phys()
1793 mapping->ppli2.ppli2_data = iprv.v2; in ia64_pal_logical_to_phys()
1818 info->num_shared = iprv.v0; in ia64_pal_cache_shared_info()
1819 info->ppli1.ppli1_data = iprv.v1; in ia64_pal_cache_shared_info()
1820 info->ppli2.ppli2_data = iprv.v2; in ia64_pal_cache_shared_info()