arm64/kernel/entry.S

33 	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 	.if	\el == 0
65 	tbnz	x0, #THREAD_SHIFT, 0f
70 0:
126 	nop					// Patched to SMC/HVC #0
199 	.if	\el == 0
205 	stp	x0, x1, [sp, #16 * 0]
216 	stp	x22, x23, [sp, #16 * 11]
221 	.if	\el == 0
236 	check_mte_async_tcf x22, x23, x0
250 	__ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
260 	apply_ssbd 1, x22, x23
262 	mte_set_kernel_gcr x22, x23
281 	.endif /* \el == 0 */
283 	mrs	x23, spsr_el1
291 	.if \el == 0
304 	stp	x22, x23, [sp, #S_PC]
307 	.if	\el == 0
331 	 * x23 - aborted PSTATE
336 	.if	\el != 0
364 	.if	\el == 0
365 	ldr	x23, [sp, #S_SP]		// load return stack pointer
366 	msr	sp_el0, x23
409 	apply_ssbd 0, x0, x1
414 	ldp	x0, x1, [sp, #16 * 0]
425 	ldp	x22, x23, [sp, #16 * 11]
430 	.if	\el == 0
478 	orr	x23, x23, #PSR_PAN_BIT		// Set the emulated PAN in the saved SPSR
480 	and	x23, x23, #~PSR_PAN_BIT		// Clear the emulated PAN in the saved SPSR
493 1:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
531 	kernel_ventry	0, t, 64, sync		// Synchronous 64-bit EL0
532 	kernel_ventry	0, t, 64, irq		// IRQ 64-bit EL0
533 	kernel_ventry	0, t, 64, fiq		// FIQ 64-bit EL0
534 	kernel_ventry	0, t, 64, error		// Error 64-bit EL0
536 	kernel_ventry	0, t, 32, sync		// Synchronous 32-bit EL0
537 	kernel_ventry	0, t, 32, irq		// IRQ 32-bit EL0
538 	kernel_ventry	0, t, 32, fiq		// FIQ 32-bit EL0
539 	kernel_ventry	0, t, 32, error		// Error 32-bit EL0
578 	.if \el == 0
599 	entry_handler	0, t, 64, sync
600 	entry_handler	0, t, 64, irq
601 	entry_handler	0, t, 64, fiq
602 	entry_handler	0, t, 64, error
604 	entry_handler	0, t, 32, sync
605 	entry_handler	0, t, 32, irq
606 	entry_handler	0, t, 32, fiq
607 	entry_handler	0, t, 32, error
619 	kernel_exit 0
674 	 * instruction to load the upper 16 bits (which must be 0xFFFF).
682 #define BHB_MITIGATION_NONE	0
745 	.space	0x400
798 	tramp_ventry	.Lvector_start\@, 64, 0, \bhb
801 	tramp_ventry	.Lvector_start\@, 32, 0, \bhb
832 	stp	x23, x24, [x8], #16
840 	ldp	x23, x24, [x8], #16
912 	smc	#0
914 99:	hvc	#0
988 	stp     x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1038 	and     x0, x3, #0xc