Lines Matching +full:5 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
36 #define Op2_shift 5
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
115 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
117 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
119 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
120 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
121 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
122 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
123 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
124 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
125 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
127 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
128 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
129 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
131 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
132 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
133 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
135 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
136 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
137 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
139 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
141 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
142 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
143 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
145 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
146 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
147 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
149 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
150 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
151 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
154 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
164 #include "asm/sysreg-defs.h"
175 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
177 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
188 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
189 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
190 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
193 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
195 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
210 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
211 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
212 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
218 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
219 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
220 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
221 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
225 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
226 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
230 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
235 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
236 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
237 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
238 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
239 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
240 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
241 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
244 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
253 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
254 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
255 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
256 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
268 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
274 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
278 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
303 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
304 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
305 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
307 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
308 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
309 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
310 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
311 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
312 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
313 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
314 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
315 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
316 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
317 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
318 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
319 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
320 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
321 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
323 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
348 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
378 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
380 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
386 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
388 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
390 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
394 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
406 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
415 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
417 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
426 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
435 * n: 0-15
441 * n: 0-15
444 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
445 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
446 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
447 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
458 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
480 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
483 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
491 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
504 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
505 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
506 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
507 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
508 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
509 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
510 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
540 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
541 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
549 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
551 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
559 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
561 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
570 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
571 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
572 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
573 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
574 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
575 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
576 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
577 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
578 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
579 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
580 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
581 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
582 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
583 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
584 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
585 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
586 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
587 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
588 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
589 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
595 #define AT_CRn 7
606 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
608 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
615 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
616 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
619 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
620 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
625 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
626 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
627 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
628 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
629 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
630 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
633 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
634 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
635 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
636 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
637 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
638 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
639 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
640 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
645 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
646 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
649 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
650 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
655 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
656 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
657 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
663 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
664 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
665 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
666 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
667 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
668 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
669 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
670 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
673 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
678 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
681 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
685 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
692 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
694 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
695 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
696 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
698 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
699 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
700 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
701 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
702 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
703 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
727 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
739 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
740 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
741 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
742 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
743 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
773 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
881 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
907 #define TRFCR_ELx_TS_SHIFT 5
922 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
956 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
958 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
968 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
970 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1090 * set mask are set. Other bits are left as-is.