include/asm/pgtable-hwdef.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
11  * Number of page-table levels required to address 'va_bits' wide
12  * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
13  * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
15  *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
17  * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
22  *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
26 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
30  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
33  * ((4 - n) - 1) levels of translation excluding the offset within the page.
36  *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
39  *   (4 - n) * (PAGE_SHIFT - 3) + 3
41 #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)
43 #define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))
50 #define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
51 #define PMD_MASK		(~(PMD_SIZE-1))
52 #define PTRS_PER_PMD		(1 << (PAGE_SHIFT - 3))
56  * PUD_SHIFT determines the size a level 1 page table entry can map.
59 #define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
60 #define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
61 #define PUD_MASK		(~(PUD_SIZE-1))
62 #define PTRS_PER_PUD		(1 << (PAGE_SHIFT - 3))
66  * PGDIR_SHIFT determines the size a top-level page table entry can map
67  * (depending on the configuration, this level can be 0, 1 or 2).
69 #define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
70 #define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
71 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
72 #define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
78 #define CONT_PTES		(1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
80 #define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
83 #define CONT_PMDS		(1 << (CONT_PMD_SHIFT - PMD_SHIFT))
85 #define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
93 #define P4D_TABLE_BIT		(_AT(p4dval_t, 1) << 1)
95 #define P4D_TYPE_SECT		(_AT(p4dval_t, 1) << 0)
96 #define P4D_SECT_RDONLY		(_AT(p4dval_t, 1) << 7)		/* AP[2] */
97 #define P4D_TABLE_PXN		(_AT(p4dval_t, 1) << 59)
98 #define P4D_TABLE_UXN		(_AT(p4dval_t, 1) << 60)
101  * Level 1 descriptor (PUD).
104 #define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
106 #define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)
107 #define PUD_SECT_RDONLY		(_AT(pudval_t, 1) << 7)		/* AP[2] */
108 #define PUD_TABLE_PXN		(_AT(pudval_t, 1) << 59)
109 #define PUD_TABLE_UXN		(_AT(pudval_t, 1) << 60)
116 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
117 #define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
122 #define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
123 #define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
124 #define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
126 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
127 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
128 #define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
129 #define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
130 #define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)
131 #define PMD_TABLE_PXN		(_AT(pmdval_t, 1) << 59)
132 #define PMD_TABLE_UXN		(_AT(pmdval_t, 1) << 60)
143 #define PTE_VALID		(_AT(pteval_t, 1) << 0)
146 #define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
147 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
148 #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
149 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
150 #define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
151 #define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
152 #define PTE_GP			(_AT(pteval_t, 1) << 50)	/* BTI guarded */
153 #define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
154 #define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
155 #define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
156 #define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
158 #define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
176 #define PTE_PI_IDX_0	6	/* AP[1], USER */
182  * Memory Attribute override for Stage-2 (MemAttr[3:0])
190 #define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
192 #define TTBR_CNP_BIT		(UL(1) << 0)
199 #define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
200 #define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
203 #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
204 #define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
207 #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
209 #define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
210 #define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
211 #define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
212 #define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
213 #define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
216 #define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
218 #define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
219 #define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
220 #define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
221 #define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
222 #define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)
232 #define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
233 #define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
234 #define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
235 #define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
236 #define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)
239 #define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
240 #define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
241 #define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
242 #define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
243 #define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)
252 #define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
253 #define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)
256 #define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
257 #define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
261 #define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
262 #define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
263 #define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
264 #define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
267 #define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
268 #define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
269 #define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
270 #define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
273 #define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
274 #define TCR_A1			(UL(1) << 22)
275 #define TCR_ASID16		(UL(1) << 36)
276 #define TCR_TBI0		(UL(1) << 37)
277 #define TCR_TBI1		(UL(1) << 38)
278 #define TCR_HA			(UL(1) << 39)
279 #define TCR_HD			(UL(1) << 40)
280 #define TCR_TBID1		(UL(1) << 52)
281 #define TCR_NFD0		(UL(1) << 53)
282 #define TCR_NFD1		(UL(1) << 54)
283 #define TCR_E0PD0		(UL(1) << 55)
284 #define TCR_E0PD1		(UL(1) << 56)
285 #define TCR_TCMA0		(UL(1) << 57)
286 #define TCR_TCMA1		(UL(1) << 58)
293  * TTBR_ELx[1] is RES0 in this configuration.
299 /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
300 #define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
301 				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)