include/asm/kvm_arm.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2012,2013 - ARM Ltd
17 #define HCR_TID5	(UL(1) << 58)
18 #define HCR_DCT		(UL(1) << 57)
20 #define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)
21 #define HCR_TTLBOS	(UL(1) << 55)
22 #define HCR_TTLBIS	(UL(1) << 54)
23 #define HCR_ENSCXT	(UL(1) << 53)
24 #define HCR_TOCU	(UL(1) << 52)
25 #define HCR_AMVOFFEN	(UL(1) << 51)
26 #define HCR_TICAB	(UL(1) << 50)
27 #define HCR_TID4	(UL(1) << 49)
28 #define HCR_FIEN	(UL(1) << 47)
29 #define HCR_FWB		(UL(1) << 46)
30 #define HCR_NV2		(UL(1) << 45)
31 #define HCR_AT		(UL(1) << 44)
32 #define HCR_NV1		(UL(1) << 43)
33 #define HCR_NV		(UL(1) << 42)
34 #define HCR_API		(UL(1) << 41)
35 #define HCR_APK		(UL(1) << 40)
36 #define HCR_TEA		(UL(1) << 37)
37 #define HCR_TERR	(UL(1) << 36)
38 #define HCR_TLOR	(UL(1) << 35)
39 #define HCR_E2H		(UL(1) << 34)
40 #define HCR_ID		(UL(1) << 33)
41 #define HCR_CD		(UL(1) << 32)
43 #define HCR_RW		(UL(1) << HCR_RW_SHIFT)
44 #define HCR_TRVM	(UL(1) << 30)
45 #define HCR_HCD		(UL(1) << 29)
46 #define HCR_TDZ		(UL(1) << 28)
47 #define HCR_TGE		(UL(1) << 27)
48 #define HCR_TVM		(UL(1) << 26)
49 #define HCR_TTLB	(UL(1) << 25)
50 #define HCR_TPU		(UL(1) << 24)
51 #define HCR_TPC		(UL(1) << 23) /* HCR_TPCP if FEAT_DPB */
52 #define HCR_TSW		(UL(1) << 22)
53 #define HCR_TACR	(UL(1) << 21)
54 #define HCR_TIDCP	(UL(1) << 20)
55 #define HCR_TSC		(UL(1) << 19)
56 #define HCR_TID3	(UL(1) << 18)
57 #define HCR_TID2	(UL(1) << 17)
58 #define HCR_TID1	(UL(1) << 16)
59 #define HCR_TID0	(UL(1) << 15)
60 #define HCR_TWE		(UL(1) << 14)
61 #define HCR_TWI		(UL(1) << 13)
62 #define HCR_DC		(UL(1) << 12)
64 #define HCR_BSU_IS	(UL(1) << 10)
65 #define HCR_FB		(UL(1) << 9)
66 #define HCR_VSE		(UL(1) << 8)
67 #define HCR_VI		(UL(1) << 7)
68 #define HCR_VF		(UL(1) << 6)
69 #define HCR_AMO		(UL(1) << 5)
70 #define HCR_IMO		(UL(1) << 4)
71 #define HCR_FMO		(UL(1) << 3)
72 #define HCR_PTW		(UL(1) << 2)
73 #define HCR_SWIO	(UL(1) << 1)
74 #define HCR_VM		(UL(1) << 0)
75 #define HCR_RES0	((UL(1) << 48) | (UL(1) << 39))
109 #define TCR_EL2_RES1		((1U << 31) | (1 << 23))
110 #define TCR_EL2_TBI		(1 << 20)
123 #define VTCR_EL2_RES1		(1U << 31)
124 #define VTCR_EL2_HD		(1 << 22)
125 #define VTCR_EL2_HA		(1 << 21)
143 #define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)
148  * We configure the Stage-2 page tables to always restrict the IPA space to be
167  *	-----------------------------------------
169  *	------------------------------------------
170  *	| Level: 0		|  2   |   -     |
171  *	------------------------------------------
172  *	| Level: 1		|  1   |   2     |
173  *	------------------------------------------
174  *	| Level: 2		|  0   |   1     |
175  *	------------------------------------------
176  *	| Level: 3		|  -   |   0     |
177  *	------------------------------------------
181  *	SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
188  * Entry_Level = 4 - Number_of_levels.
194 #define VTCR_EL2_TGRAN_SL0_BASE		3UL
199 #define VTCR_EL2_TGRAN_SL0_BASE		3UL
204 #define VTCR_EL2_TGRAN_SL0_BASE		2UL
209 	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
211 	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
216 #define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
219  * ARM VMSAv8-64 defines an algorithm for finding the translation table
235  *    x = Magic_N - T0SZ
240  *	--------------------------------------------
242  *	--------------------------------------------
243  *	| Level: 0 (4 levels)	| 28   |  -  |  -  |
244  *	--------------------------------------------
245  *	| Level: 1 (3 levels)	| 37   | 31  | 25  |
246  *	--------------------------------------------
248  *	--------------------------------------------
249  *	| Level: 3 (1 level)	| -    | 53  | 51  |
250  *	--------------------------------------------
254  *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
256  * where Number_of_levels = (4 - Level). We are only interested in the
259  * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
261  *	x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
262  *	  = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
268  * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
271  *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
272  *		     = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
276  *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
281 #define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))
283 #define VTTBR_CNP_BIT     (UL(1))
284 #define VTTBR_VMID_SHIFT  (UL(48))
285 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
288 #define HSTR_EL2_T(x)	(1 << x)
294 #define CPTR_EL2_TCPAC	(1U << 31)
295 #define CPTR_EL2_TAM	(1 << 30)
296 #define CPTR_EL2_TTA	(1 << 20)
297 #define CPTR_EL2_TSM	(1 << 12)
298 #define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)
299 #define CPTR_EL2_TZ	(1 << 8)
307 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
308 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
309 #define MDCR_EL2_HPMFZS		(UL(1) << 36)
310 #define MDCR_EL2_HPMFZO		(UL(1) << 29)
311 #define MDCR_EL2_MTPME		(UL(1) << 28)
312 #define MDCR_EL2_TDCC		(UL(1) << 27)
313 #define MDCR_EL2_HLP		(UL(1) << 26)
314 #define MDCR_EL2_HCCD		(UL(1) << 23)
315 #define MDCR_EL2_TTRF		(UL(1) << 19)
316 #define MDCR_EL2_HPMD		(UL(1) << 17)
317 #define MDCR_EL2_TPMS		(UL(1) << 14)
318 #define MDCR_EL2_E2PB_MASK	(UL(0x3))
319 #define MDCR_EL2_E2PB_SHIFT	(UL(12))
320 #define MDCR_EL2_TDRA		(UL(1) << 11)
321 #define MDCR_EL2_TDOSA		(UL(1) << 10)
322 #define MDCR_EL2_TDA		(UL(1) << 9)
323 #define MDCR_EL2_TDE		(UL(1) << 8)
324 #define MDCR_EL2_HPME		(UL(1) << 7)
325 #define MDCR_EL2_TPM		(UL(1) << 6)
326 #define MDCR_EL2_TPMCR		(UL(1) << 5)
327 #define MDCR_EL2_HPMN_MASK	(UL(0x1F))
377 #define HPFAR_MASK	(~UL(0xf))
380  *	PAR	[PA_Shift - 1	: 12] = PA	[PA_Shift - 1 : 12]
381  *	HPFAR	[PA_Shift - 9	: 4]  = FIPA	[PA_Shift - 1 : 12]
388 	(((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
403 #define CPACR_EL1_TTA		(1 << 28)
413 	{ PSR_AA32_MODE_USR,	"32-bit USR" },	\
414 	{ PSR_AA32_MODE_FIQ,	"32-bit FIQ" },	\
415 	{ PSR_AA32_MODE_IRQ,	"32-bit IRQ" },	\
416 	{ PSR_AA32_MODE_SVC,	"32-bit SVC" },	\
417 	{ PSR_AA32_MODE_ABT,	"32-bit ABT" },	\
418 	{ PSR_AA32_MODE_HYP,	"32-bit HYP" },	\
419 	{ PSR_AA32_MODE_UND,	"32-bit UND" },	\
420 	{ PSR_AA32_MODE_SYS,	"32-bit SYS" }