include/asm/esr.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2013 - ARM Ltd
13 #define ESR_ELx_EC_UNKNOWN	UL(0x00)
14 #define ESR_ELx_EC_WFx		UL(0x01)
16 #define ESR_ELx_EC_CP15_32	UL(0x03)
17 #define ESR_ELx_EC_CP15_64	UL(0x04)
18 #define ESR_ELx_EC_CP14_MR	UL(0x05)
19 #define ESR_ELx_EC_CP14_LS	UL(0x06)
20 #define ESR_ELx_EC_FP_ASIMD	UL(0x07)
21 #define ESR_ELx_EC_CP10_ID	UL(0x08)	/* EL2 only */
22 #define ESR_ELx_EC_PAC		UL(0x09)	/* EL2 and above */
23 /* Unallocated EC: 0x0A - 0x0B */
24 #define ESR_ELx_EC_CP14_64	UL(0x0C)
25 #define ESR_ELx_EC_BTI		UL(0x0D)
26 #define ESR_ELx_EC_ILL		UL(0x0E)
27 /* Unallocated EC: 0x0F - 0x10 */
28 #define ESR_ELx_EC_SVC32	UL(0x11)
29 #define ESR_ELx_EC_HVC32	UL(0x12)	/* EL2 only */
30 #define ESR_ELx_EC_SMC32	UL(0x13)	/* EL2 and above */
32 #define ESR_ELx_EC_SVC64	UL(0x15)
33 #define ESR_ELx_EC_HVC64	UL(0x16)	/* EL2 and above */
34 #define ESR_ELx_EC_SMC64	UL(0x17)	/* EL2 and above */
35 #define ESR_ELx_EC_SYS64	UL(0x18)
36 #define ESR_ELx_EC_SVE		UL(0x19)
37 #define ESR_ELx_EC_ERET		UL(0x1a)	/* EL2 only */
39 #define ESR_ELx_EC_FPAC		UL(0x1C)	/* EL1 and above */
40 #define ESR_ELx_EC_SME		UL(0x1D)
42 #define ESR_ELx_EC_IMP_DEF	UL(0x1f)	/* EL3 only */
43 #define ESR_ELx_EC_IABT_LOW	UL(0x20)
44 #define ESR_ELx_EC_IABT_CUR	UL(0x21)
45 #define ESR_ELx_EC_PC_ALIGN	UL(0x22)
47 #define ESR_ELx_EC_DABT_LOW	UL(0x24)
48 #define ESR_ELx_EC_DABT_CUR	UL(0x25)
49 #define ESR_ELx_EC_SP_ALIGN	UL(0x26)
50 #define ESR_ELx_EC_MOPS		UL(0x27)
51 #define ESR_ELx_EC_FP_EXC32	UL(0x28)
52 /* Unallocated EC: 0x29 - 0x2B */
53 #define ESR_ELx_EC_FP_EXC64	UL(0x2C)
54 /* Unallocated EC: 0x2D - 0x2E */
55 #define ESR_ELx_EC_SERROR	UL(0x2F)
56 #define ESR_ELx_EC_BREAKPT_LOW	UL(0x30)
57 #define ESR_ELx_EC_BREAKPT_CUR	UL(0x31)
58 #define ESR_ELx_EC_SOFTSTP_LOW	UL(0x32)
59 #define ESR_ELx_EC_SOFTSTP_CUR	UL(0x33)
60 #define ESR_ELx_EC_WATCHPT_LOW	UL(0x34)
61 #define ESR_ELx_EC_WATCHPT_CUR	UL(0x35)
62 /* Unallocated EC: 0x36 - 0x37 */
63 #define ESR_ELx_EC_BKPT32	UL(0x38)
65 #define ESR_ELx_EC_VECTOR32	UL(0x3A)	/* EL2 only */
67 #define ESR_ELx_EC_BRK64	UL(0x3C)
68 /* Unallocated EC: 0x3D - 0x3F */
69 #define ESR_ELx_EC_MAX		UL(0x3F)
73 #define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
77 #define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
86 #define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
90 #define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
92 #define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
94 #define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
102 #define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
104 #define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
106 #define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
108 #define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
132 #define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
134 #define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
136 #define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
138 #define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
140 #define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
142 #define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
144 #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
148 #define ESR_ELx_TnD 		(UL(1) << ESR_ELx_TnD_SHIFT)
150 #define ESR_ELx_TagAccess	(UL(1) << ESR_ELx_TagAccess_SHIFT)
152 #define ESR_ELx_GCS 		(UL(1) << ESR_ELx_GCS_SHIFT)
154 #define ESR_ELx_Overlay		(UL(1) << ESR_ELx_Overlay_SHIFT)
156 #define ESR_ELx_DirtyBit	(UL(1) << ESR_ELx_DirtyBit_SHIFT)
161 #define ESR_ELx_CV		(UL(1) << 24)
163 #define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
164 #define ESR_ELx_WFx_ISS_RN	(UL(0x1F) << 5)
165 #define ESR_ELx_WFx_ISS_RV	(UL(1) << 2)
166 #define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)
167 #define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)
168 #define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
169 #define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
170 #define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)
172 #define DISR_EL1_IDS		(UL(1) << 24)
190 #define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
196 #define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
197 #define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
198 #define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
200 #define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
202 #define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
204 #define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
206 #define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
226  * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
241 				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
246  * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
256 #define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
297  * ISS field definitions for floating-point exception traps
303 #define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
313 #define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
314 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
315 #define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
317 #define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
319 #define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
321 #define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
339 #define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
342 #define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
345 #define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
346 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
347 #define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
357 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
371 #define ESR_ELx_SME_ISS_ILL		1
377 #define ESR_ELx_MOPS_ISS_MEM_INST	(UL(1) << 24)
378 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE	(UL(1) << 18)
379 #define ESR_ELx_MOPS_ISS_WRONG_OPTION	(UL(1) << 17)
380 #define ESR_ELx_MOPS_ISS_OPTION_A	(UL(1) << 16)
381 #define ESR_ELx_MOPS_ISS_DESTREG(esr)	(((esr) & (UL(0x1f) << 10)) >> 10)
382 #define ESR_ELx_MOPS_ISS_SRCREG(esr)	(((esr) & (UL(0x1f) << 5)) >> 5)
383 #define ESR_ELx_MOPS_ISS_SIZEREG(esr)	(((esr) & (UL(0x1f) << 0)) >> 0)