Lines Matching refs:tmp2
440 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
441 dcache_line_size \tmp1, \tmp2
442 dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup
453 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
454 icache_line_size \tmp1, \tmp2
455 sub \tmp2, \tmp1, #1
456 bic \tmp2, \start, \tmp2
458 ic ivau, \tmp2 // invalidate I line PoU
459 add \tmp2, \tmp2, \tmp1
460 cmp \tmp2, \end
473 .macro load_ttbr1, pgtbl, tmp1, tmp2
475 offset_ttbr1 \tmp1, \tmp2
487 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
493 load_ttbr1 \page_table, \tmp, \tmp2
648 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
652 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK
653 and \tmp1, \tmp1, \tmp2
654 mov_q \tmp2, MIDR_FUJITSU_ERRATUM_010001
655 cmp \tmp1, \tmp2
658 mov_q \tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001
659 bic \tcr, \tcr, \tmp2
771 .macro cond_yield, lbl:req, tmp:req, tmp2:req
785 get_this_cpu_offset \tmp2
786 ldr w\tmp, [\tmp, \tmp2]