Lines Matching +full:zynqmp +full:- +full:dpsub +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
23 compatible = "xlnx,zynqmp";
24 #address-cells = <2>;
25 #size-cells = <2>;
28 #address-cells = <1>;
29 #size-cells = <0>;
32 compatible = "arm,cortex-a53";
34 enable-method = "psci";
35 operating-points-v2 = <&cpu_opp_table>;
37 cpu-idle-states = <&CPU_SLEEP_0>;
38 next-level-cache = <&L2>;
41 cpu1: cpu@1 {
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
46 operating-points-v2 = <&cpu_opp_table>;
47 cpu-idle-states = <&CPU_SLEEP_0>;
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
58 next-level-cache = <&L2>;
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
66 operating-points-v2 = <&cpu_opp_table>;
67 cpu-idle-states = <&CPU_SLEEP_0>;
68 next-level-cache = <&L2>;
71 L2: l2-cache {
73 cache-level = <2>;
74 cache-unified;
77 idle-states {
78 entry-method = "psci";
80 CPU_SLEEP_0: cpu-sleep-0 {
81 compatible = "arm,idle-state";
82 arm,psci-suspend-param = <0x40000000>;
83 local-timer-stop;
84 entry-latency-us = <300>;
85 exit-latency-us = <600>;
86 min-residency-us = <10000>;
91 cpu_opp_table: opp-table-cpu {
92 compatible = "operating-points-v2";
93 opp-shared;
95 opp-hz = /bits/ 64 <1199999988>;
96 opp-microvolt = <1000000>;
97 clock-latency-ns = <500000>;
100 opp-hz = /bits/ 64 <599999994>;
101 opp-microvolt = <1000000>;
102 clock-latency-ns = <500000>;
105 opp-hz = /bits/ 64 <399999996>;
106 opp-microvolt = <1000000>;
107 clock-latency-ns = <500000>;
110 opp-hz = /bits/ 64 <299999997>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <500000>;
116 reserved-memory {
117 #address-cells = <2>;
118 #size-cells = <2>;
122 no-map;
127 no-map;
133 bootph-all;
134 compatible = "xlnx,zynqmp-ipi-mailbox";
135 interrupt-parent = <&gic>;
137 xlnx,ipi-id = <0>;
138 #address-cells = <2>;
139 #size-cells = <2>;
143 bootph-all;
148 reg-names = "local_request_region",
152 #mbox-cells = <1>;
153 xlnx,ipi-id = <4>;
160 bootph-all;
164 compatible = "arm,armv8-pmuv3";
165 interrupt-parent = <&gic>;
170 interrupt-affinity = <&cpu0>,
177 compatible = "arm,psci-0.2";
182 zynqmp_firmware: zynqmp-firmware {
183 compatible = "xlnx,zynqmp-firmware";
184 #power-domain-cells = <1>;
186 bootph-all;
188 zynqmp_power: zynqmp-power {
189 bootph-all;
190 compatible = "xlnx,zynqmp-power";
191 interrupt-parent = <&gic>;
193 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
194 mbox-names = "tx", "rx";
198 compatible = "xlnx,zynqmp-nvmem-fw";
199 #address-cells = <1>;
200 #size-cells = <1>;
208 compatible = "xlnx,zynqmp-pcap-fpga";
211 xlnx_aes: zynqmp-aes {
212 compatible = "xlnx,zynqmp-aes";
215 zynqmp_reset: reset-controller {
216 compatible = "xlnx,zynqmp-reset";
217 #reset-cells = <1>;
221 compatible = "xlnx,zynqmp-pinctrl";
226 compatible = "xlnx,zynqmp-gpio-modepin";
227 gpio-controller;
228 #gpio-cells = <2>;
234 compatible = "arm,armv8-timer";
235 interrupt-parent = <&gic>;
242 fpga_full: fpga-full {
243 compatible = "fpga-region";
244 fpga-mgr = <&zynqmp_pcap>;
245 #address-cells = <2>;
246 #size-cells = <2>;
251 compatible = "xlnx,zynqmp-r5fss";
252 xlnx,cluster-mode = <1>;
254 r5f-0 {
255 compatible = "xlnx,zynqmp-r5f";
256 power-domains = <&zynqmp_firmware PD_RPU_0>;
257 memory-region = <&rproc_0_fw_image>;
260 r5f-1 {
261 compatible = "xlnx,zynqmp-r5f";
262 power-domains = <&zynqmp_firmware PD_RPU_1>;
263 memory-region = <&rproc_1_fw_image>;
268 compatible = "simple-bus";
269 bootph-all;
270 #address-cells = <2>;
271 #size-cells = <2>;
275 compatible = "xlnx,zynq-can-1.0";
277 clock-names = "can_clk", "pclk";
280 interrupt-parent = <&gic>;
281 tx-fifo-depth = <0x40>;
282 rx-fifo-depth = <0x40>;
283 power-domains = <&zynqmp_firmware PD_CAN_0>;
287 compatible = "xlnx,zynq-can-1.0";
289 clock-names = "can_clk", "pclk";
292 interrupt-parent = <&gic>;
293 tx-fifo-depth = <0x40>;
294 rx-fifo-depth = <0x40>;
295 power-domains = <&zynqmp_firmware PD_CAN_1>;
299 compatible = "arm,cci-400";
303 #address-cells = <1>;
304 #size-cells = <1>;
307 compatible = "arm,cci-400-pmu,r1";
309 interrupt-parent = <&gic>;
319 fpd_dma_chan1: dma-controller@fd500000 {
321 compatible = "xlnx,zynqmp-dma-1.0";
323 interrupt-parent = <&gic>;
325 clock-names = "clk_main", "clk_apb";
326 #dma-cells = <1>;
327 xlnx,bus-width = <128>;
329 power-domains = <&zynqmp_firmware PD_GDMA>;
332 fpd_dma_chan2: dma-controller@fd510000 {
334 compatible = "xlnx,zynqmp-dma-1.0";
336 interrupt-parent = <&gic>;
338 clock-names = "clk_main", "clk_apb";
339 #dma-cells = <1>;
340 xlnx,bus-width = <128>;
342 power-domains = <&zynqmp_firmware PD_GDMA>;
345 fpd_dma_chan3: dma-controller@fd520000 {
347 compatible = "xlnx,zynqmp-dma-1.0";
349 interrupt-parent = <&gic>;
351 clock-names = "clk_main", "clk_apb";
352 #dma-cells = <1>;
353 xlnx,bus-width = <128>;
355 power-domains = <&zynqmp_firmware PD_GDMA>;
358 fpd_dma_chan4: dma-controller@fd530000 {
360 compatible = "xlnx,zynqmp-dma-1.0";
362 interrupt-parent = <&gic>;
364 clock-names = "clk_main", "clk_apb";
365 #dma-cells = <1>;
366 xlnx,bus-width = <128>;
368 power-domains = <&zynqmp_firmware PD_GDMA>;
371 fpd_dma_chan5: dma-controller@fd540000 {
373 compatible = "xlnx,zynqmp-dma-1.0";
375 interrupt-parent = <&gic>;
377 clock-names = "clk_main", "clk_apb";
378 #dma-cells = <1>;
379 xlnx,bus-width = <128>;
381 power-domains = <&zynqmp_firmware PD_GDMA>;
384 fpd_dma_chan6: dma-controller@fd550000 {
386 compatible = "xlnx,zynqmp-dma-1.0";
388 interrupt-parent = <&gic>;
390 clock-names = "clk_main", "clk_apb";
391 #dma-cells = <1>;
392 xlnx,bus-width = <128>;
394 power-domains = <&zynqmp_firmware PD_GDMA>;
397 fpd_dma_chan7: dma-controller@fd560000 {
399 compatible = "xlnx,zynqmp-dma-1.0";
401 interrupt-parent = <&gic>;
403 clock-names = "clk_main", "clk_apb";
404 #dma-cells = <1>;
405 xlnx,bus-width = <128>;
407 power-domains = <&zynqmp_firmware PD_GDMA>;
410 fpd_dma_chan8: dma-controller@fd570000 {
412 compatible = "xlnx,zynqmp-dma-1.0";
414 interrupt-parent = <&gic>;
416 clock-names = "clk_main", "clk_apb";
417 #dma-cells = <1>;
418 xlnx,bus-width = <128>;
420 power-domains = <&zynqmp_firmware PD_GDMA>;
423 gic: interrupt-controller@f9010000 {
424 compatible = "arm,gic-400";
425 #interrupt-cells = <3>;
430 interrupt-controller;
431 interrupt-parent = <&gic>;
437 compatible = "xlnx,zynqmp-mali", "arm,mali-400";
439 interrupt-parent = <&gic>;
446 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
447 clock-names = "bus", "core";
448 power-domains = <&zynqmp_firmware PD_GPU>;
455 lpd_dma_chan1: dma-controller@ffa80000 {
457 compatible = "xlnx,zynqmp-dma-1.0";
459 interrupt-parent = <&gic>;
461 clock-names = "clk_main", "clk_apb";
462 #dma-cells = <1>;
463 xlnx,bus-width = <64>;
465 power-domains = <&zynqmp_firmware PD_ADMA>;
468 lpd_dma_chan2: dma-controller@ffa90000 {
470 compatible = "xlnx,zynqmp-dma-1.0";
472 interrupt-parent = <&gic>;
474 clock-names = "clk_main", "clk_apb";
475 #dma-cells = <1>;
476 xlnx,bus-width = <64>;
478 power-domains = <&zynqmp_firmware PD_ADMA>;
481 lpd_dma_chan3: dma-controller@ffaa0000 {
483 compatible = "xlnx,zynqmp-dma-1.0";
485 interrupt-parent = <&gic>;
487 clock-names = "clk_main", "clk_apb";
488 #dma-cells = <1>;
489 xlnx,bus-width = <64>;
491 power-domains = <&zynqmp_firmware PD_ADMA>;
494 lpd_dma_chan4: dma-controller@ffab0000 {
496 compatible = "xlnx,zynqmp-dma-1.0";
498 interrupt-parent = <&gic>;
500 clock-names = "clk_main", "clk_apb";
501 #dma-cells = <1>;
502 xlnx,bus-width = <64>;
504 power-domains = <&zynqmp_firmware PD_ADMA>;
507 lpd_dma_chan5: dma-controller@ffac0000 {
509 compatible = "xlnx,zynqmp-dma-1.0";
511 interrupt-parent = <&gic>;
513 clock-names = "clk_main", "clk_apb";
514 #dma-cells = <1>;
515 xlnx,bus-width = <64>;
517 power-domains = <&zynqmp_firmware PD_ADMA>;
520 lpd_dma_chan6: dma-controller@ffad0000 {
522 compatible = "xlnx,zynqmp-dma-1.0";
524 interrupt-parent = <&gic>;
526 clock-names = "clk_main", "clk_apb";
527 #dma-cells = <1>;
528 xlnx,bus-width = <64>;
530 power-domains = <&zynqmp_firmware PD_ADMA>;
533 lpd_dma_chan7: dma-controller@ffae0000 {
535 compatible = "xlnx,zynqmp-dma-1.0";
537 interrupt-parent = <&gic>;
539 clock-names = "clk_main", "clk_apb";
540 #dma-cells = <1>;
541 xlnx,bus-width = <64>;
543 power-domains = <&zynqmp_firmware PD_ADMA>;
546 lpd_dma_chan8: dma-controller@ffaf0000 {
548 compatible = "xlnx,zynqmp-dma-1.0";
550 interrupt-parent = <&gic>;
552 clock-names = "clk_main", "clk_apb";
553 #dma-cells = <1>;
554 xlnx,bus-width = <64>;
556 power-domains = <&zynqmp_firmware PD_ADMA>;
559 mc: memory-controller@fd070000 {
560 compatible = "xlnx,zynqmp-ddrc-2.40a";
562 interrupt-parent = <&gic>;
566 nand0: nand-controller@ff100000 {
567 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
570 clock-names = "controller", "bus";
571 interrupt-parent = <&gic>;
573 #address-cells = <1>;
574 #size-cells = <0>;
576 power-domains = <&zynqmp_firmware PD_NAND>;
580 compatible = "xlnx,zynqmp-gem", "cdns,gem";
582 interrupt-parent = <&gic>;
586 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
587 #address-cells = <1>;
588 #size-cells = <0>;
590 power-domains = <&zynqmp_firmware PD_ETH_0>;
592 reset-names = "gem0_rst";
596 compatible = "xlnx,zynqmp-gem", "cdns,gem";
598 interrupt-parent = <&gic>;
602 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
603 #address-cells = <1>;
604 #size-cells = <0>;
606 power-domains = <&zynqmp_firmware PD_ETH_1>;
608 reset-names = "gem1_rst";
612 compatible = "xlnx,zynqmp-gem", "cdns,gem";
614 interrupt-parent = <&gic>;
618 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
619 #address-cells = <1>;
620 #size-cells = <0>;
622 power-domains = <&zynqmp_firmware PD_ETH_2>;
624 reset-names = "gem2_rst";
628 compatible = "xlnx,zynqmp-gem", "cdns,gem";
630 interrupt-parent = <&gic>;
634 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
635 #address-cells = <1>;
636 #size-cells = <0>;
638 power-domains = <&zynqmp_firmware PD_ETH_3>;
640 reset-names = "gem3_rst";
644 compatible = "xlnx,zynqmp-gpio-1.0";
646 #gpio-cells = <0x2>;
647 gpio-controller;
648 interrupt-parent = <&gic>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
653 power-domains = <&zynqmp_firmware PD_GPIO>;
657 compatible = "cdns,i2c-r1p14";
659 interrupt-parent = <&gic>;
661 clock-frequency = <400000>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 power-domains = <&zynqmp_firmware PD_I2C_0>;
669 compatible = "cdns,i2c-r1p14";
671 interrupt-parent = <&gic>;
673 clock-frequency = <400000>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 power-domains = <&zynqmp_firmware PD_I2C_1>;
681 compatible = "xlnx,nwl-pcie-2.11";
683 #address-cells = <3>;
684 #size-cells = <2>;
685 #interrupt-cells = <1>;
686 msi-controller;
688 interrupt-parent = <&gic>;
694 interrupt-names = "misc", "dummy", "intx",
696 msi-parent = <&pcie>;
700 reg-names = "breg", "pcireg", "cfg";
701 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
710 power-domains = <&zynqmp_firmware PD_PCIE>;
711 pcie_intc: legacy-interrupt-controller {
712 interrupt-controller;
713 #address-cells = <0>;
714 #interrupt-cells = <1>;
719 bootph-all;
720 compatible = "xlnx,zynqmp-qspi-1.0";
722 clock-names = "ref_clk", "pclk";
724 interrupt-parent = <&gic>;
725 num-cs = <1>;
728 #address-cells = <1>;
729 #size-cells = <0>;
731 power-domains = <&zynqmp_firmware PD_QSPI>;
735 compatible = "xlnx,zynqmp-psgtr-v1.1";
739 reg-names = "serdes", "siou";
740 #phy-cells = <4>;
744 compatible = "xlnx,zynqmp-rtc";
747 interrupt-parent = <&gic>;
750 interrupt-names = "alarm", "sec";
755 compatible = "ceva,ahci-1v84";
758 interrupt-parent = <&gic>;
760 power-domains = <&zynqmp_firmware PD_SATA>;
767 bootph-all;
768 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
770 interrupt-parent = <&gic>;
773 clock-names = "clk_xin", "clk_ahb";
775 #clock-cells = <1>;
776 clock-output-names = "clk_out_sd0", "clk_in_sd0";
777 power-domains = <&zynqmp_firmware PD_SD_0>;
782 bootph-all;
783 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
785 interrupt-parent = <&gic>;
788 clock-names = "clk_xin", "clk_ahb";
790 #clock-cells = <1>;
791 clock-output-names = "clk_out_sd1", "clk_in_sd1";
792 power-domains = <&zynqmp_firmware PD_SD_1>;
797 compatible = "arm,mmu-500";
799 #iommu-cells = <1>;
801 #global-interrupts = <1>;
802 interrupt-parent = <&gic>;
823 compatible = "cdns,spi-r1p6";
825 interrupt-parent = <&gic>;
828 clock-names = "ref_clk", "pclk";
829 #address-cells = <1>;
830 #size-cells = <0>;
831 power-domains = <&zynqmp_firmware PD_SPI_0>;
835 compatible = "cdns,spi-r1p6";
837 interrupt-parent = <&gic>;
840 clock-names = "ref_clk", "pclk";
841 #address-cells = <1>;
842 #size-cells = <0>;
843 power-domains = <&zynqmp_firmware PD_SPI_1>;
849 interrupt-parent = <&gic>;
854 timer-width = <32>;
855 power-domains = <&zynqmp_firmware PD_TTC_0>;
861 interrupt-parent = <&gic>;
866 timer-width = <32>;
867 power-domains = <&zynqmp_firmware PD_TTC_1>;
873 interrupt-parent = <&gic>;
878 timer-width = <32>;
879 power-domains = <&zynqmp_firmware PD_TTC_2>;
885 interrupt-parent = <&gic>;
890 timer-width = <32>;
891 power-domains = <&zynqmp_firmware PD_TTC_3>;
895 bootph-all;
896 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
898 interrupt-parent = <&gic>;
901 clock-names = "uart_clk", "pclk";
902 power-domains = <&zynqmp_firmware PD_UART_0>;
906 bootph-all;
907 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
909 interrupt-parent = <&gic>;
912 clock-names = "uart_clk", "pclk";
913 power-domains = <&zynqmp_firmware PD_UART_1>;
917 #address-cells = <2>;
918 #size-cells = <2>;
920 compatible = "xlnx,zynqmp-dwc3";
922 power-domains = <&zynqmp_firmware PD_USB_0>;
926 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
927 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>;
933 interrupt-parent = <&gic>;
934 interrupt-names = "host", "peripheral", "otg";
938 clock-names = "bus_early", "ref";
940 snps,quirk-frame-length-adjustment = <0x20>;
941 snps,resume-hs-terminations;
942 /* dma-coherent; */
947 #address-cells = <2>;
948 #size-cells = <2>;
950 compatible = "xlnx,zynqmp-dwc3";
952 power-domains = <&zynqmp_firmware PD_USB_1>;
956 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
962 interrupt-parent = <&gic>;
963 interrupt-names = "host", "peripheral", "otg";
967 clock-names = "bus_early", "ref";
969 snps,quirk-frame-length-adjustment = <0x20>;
970 snps,resume-hs-terminations;
971 /* dma-coherent; */
976 compatible = "cdns,wdt-r1p2";
978 interrupt-parent = <&gic>;
981 timeout-sec = <60>;
982 reset-on-timeout;
986 compatible = "cdns,wdt-r1p2";
988 interrupt-parent = <&gic>;
991 timeout-sec = <10>;
995 compatible = "xlnx,zynqmp-ams";
997 interrupt-parent = <&gic>;
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1002 #io-channel-cells = <1>;
1005 ams_ps: ams-ps@0 {
1006 compatible = "xlnx,zynqmp-ams-ps";
1011 ams_pl: ams-pl@400 {
1012 compatible = "xlnx,zynqmp-ams-pl";
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1020 zynqmp_dpdma: dma-controller@fd4c0000 {
1021 compatible = "xlnx,zynqmp-dpdma";
1025 interrupt-parent = <&gic>;
1026 clock-names = "axi_clk";
1027 power-domains = <&zynqmp_firmware PD_DP>;
1028 #dma-cells = <1>;
1032 bootph-all;
1033 compatible = "xlnx,zynqmp-dpsub-1.7";
1039 reg-names = "dp", "blend", "av_buf", "aud";
1041 interrupt-parent = <&gic>;
1042 clock-names = "dp_apb_clk", "dp_aud_clk",
1044 power-domains = <&zynqmp_firmware PD_DP>;
1046 dma-names = "vid0", "vid1", "vid2", "gfx0";
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1059 port@1 {
1060 reg = <1>;