Lines Matching +full:0 +full:xff9905c0
29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
137 xlnx,ipi-id = <0>;
144 reg = <0x0 0xff9905c0 0x0 0x20>,
145 <0x0 0xff9905e0 0x0 0x20>,
146 <0x0 0xff990e80 0x0 0x20>,
147 <0x0 0xff990ea0 0x0 0x20>;
193 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
202 soc_revision: soc_revision@0 {
203 reg = <0x0 0x4>;
254 r5f-0 {
278 reg = <0x0 0xff060000 0x0 0x1000>;
281 tx-fifo-depth = <0x40>;
282 rx-fifo-depth = <0x40>;
290 reg = <0x0 0xff070000 0x0 0x1000>;
293 tx-fifo-depth = <0x40>;
294 rx-fifo-depth = <0x40>;
301 reg = <0x0 0xfd6e0000 0x0 0x9000>;
302 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
308 reg = <0x9000 0x5000>;
322 reg = <0x0 0xfd500000 0x0 0x1000>;
328 iommus = <&smmu 0x14e8>;
335 reg = <0x0 0xfd510000 0x0 0x1000>;
341 iommus = <&smmu 0x14e9>;
348 reg = <0x0 0xfd520000 0x0 0x1000>;
354 iommus = <&smmu 0x14ea>;
361 reg = <0x0 0xfd530000 0x0 0x1000>;
367 iommus = <&smmu 0x14eb>;
374 reg = <0x0 0xfd540000 0x0 0x1000>;
380 iommus = <&smmu 0x14ec>;
387 reg = <0x0 0xfd550000 0x0 0x1000>;
393 iommus = <&smmu 0x14ed>;
400 reg = <0x0 0xfd560000 0x0 0x1000>;
406 iommus = <&smmu 0x14ee>;
413 reg = <0x0 0xfd570000 0x0 0x1000>;
419 iommus = <&smmu 0x14ef>;
426 reg = <0x0 0xf9010000 0x0 0x10000>,
427 <0x0 0xf9020000 0x0 0x20000>,
428 <0x0 0xf9040000 0x0 0x20000>,
429 <0x0 0xf9060000 0x0 0x20000>;
438 reg = <0x0 0xfd4b0000 0x0 0x10000>;
458 reg = <0x0 0xffa80000 0x0 0x1000>;
464 iommus = <&smmu 0x868>;
471 reg = <0x0 0xffa90000 0x0 0x1000>;
477 iommus = <&smmu 0x869>;
484 reg = <0x0 0xffaa0000 0x0 0x1000>;
490 iommus = <&smmu 0x86a>;
497 reg = <0x0 0xffab0000 0x0 0x1000>;
503 iommus = <&smmu 0x86b>;
510 reg = <0x0 0xffac0000 0x0 0x1000>;
516 iommus = <&smmu 0x86c>;
523 reg = <0x0 0xffad0000 0x0 0x1000>;
529 iommus = <&smmu 0x86d>;
536 reg = <0x0 0xffae0000 0x0 0x1000>;
542 iommus = <&smmu 0x86e>;
549 reg = <0x0 0xffaf0000 0x0 0x1000>;
555 iommus = <&smmu 0x86f>;
561 reg = <0x0 0xfd070000 0x0 0x30000>;
569 reg = <0x0 0xff100000 0x0 0x1000>;
574 #size-cells = <0>;
575 iommus = <&smmu 0x872>;
585 reg = <0x0 0xff0b0000 0x0 0x1000>;
588 #size-cells = <0>;
589 iommus = <&smmu 0x874>;
601 reg = <0x0 0xff0c0000 0x0 0x1000>;
604 #size-cells = <0>;
605 iommus = <&smmu 0x875>;
617 reg = <0x0 0xff0d0000 0x0 0x1000>;
620 #size-cells = <0>;
621 iommus = <&smmu 0x876>;
633 reg = <0x0 0xff0e0000 0x0 0x1000>;
636 #size-cells = <0>;
637 iommus = <&smmu 0x877>;
646 #gpio-cells = <0x2>;
652 reg = <0x0 0xff0a0000 0x0 0x1000>;
662 reg = <0x0 0xff020000 0x0 0x1000>;
664 #size-cells = <0>;
674 reg = <0x0 0xff030000 0x0 0x1000>;
676 #size-cells = <0>;
693 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
697 reg = <0x0 0xfd0e0000 0x0 0x1000>,
698 <0x0 0xfd480000 0x0 0x1000>,
699 <0x80 0x00000000 0x0 0x1000000>;
701 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
702 …<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable mem…
703 bus-range = <0x00 0xff>;
704 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
705 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
706 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
707 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
708 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
709 iommus = <&smmu 0x4d0>;
713 #address-cells = <0>;
726 reg = <0x0 0xff0f0000 0x0 0x1000>,
727 <0x0 0xc0000000 0x0 0x8000000>;
729 #size-cells = <0>;
730 iommus = <&smmu 0x873>;
737 reg = <0x0 0xfd400000 0x0 0x40000>,
738 <0x0 0xfd3d0000 0x0 0x1000>;
746 reg = <0x0 0xffa60000 0x0 0x100>;
751 calibration = <0x7FFF>;
757 reg = <0x0 0xfd0c0000 0x0 0x2000>;
762 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
763 <&smmu 0x4c2>, <&smmu 0x4c3>;
772 reg = <0x0 0xff160000 0x0 0x1000>;
774 iommus = <&smmu 0x870>;
787 reg = <0x0 0xff170000 0x0 0x1000>;
789 iommus = <&smmu 0x871>;
798 reg = <0x0 0xfd800000 0x0 0x20000>;
827 reg = <0x0 0xff040000 0x0 0x1000>;
830 #size-cells = <0>;
839 reg = <0x0 0xff050000 0x0 0x1000>;
842 #size-cells = <0>;
853 reg = <0x0 0xff110000 0x0 0x1000>;
865 reg = <0x0 0xff120000 0x0 0x1000>;
877 reg = <0x0 0xff130000 0x0 0x1000>;
889 reg = <0x0 0xff140000 0x0 0x1000>;
900 reg = <0x0 0xff000000 0x0 0x1000>;
911 reg = <0x0 0xff010000 0x0 0x1000>;
921 reg = <0x0 0xff9d0000 0x0 0x100>;
932 reg = <0x0 0xfe200000 0x0 0x40000>;
939 iommus = <&smmu 0x860>;
940 snps,quirk-frame-length-adjustment = <0x20>;
951 reg = <0x0 0xff9e0000 0x0 0x100>;
961 reg = <0x0 0xfe300000 0x0 0x40000>;
968 iommus = <&smmu 0x861>;
969 snps,quirk-frame-length-adjustment = <0x20>;
980 reg = <0x0 0xfd4d0000 0x0 0x1000>;
990 reg = <0x0 0xff150000 0x0 0x1000>;
999 reg = <0x0 0xffa50000 0x0 0x800>;
1003 ranges = <0 0 0xffa50800 0x800>;
1005 ams_ps: ams-ps@0 {
1008 reg = <0x0 0x400>;
1014 reg = <0x400 0x400>;
1016 #size-cells = <0>;
1023 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1035 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1036 <0x0 0xfd4aa000 0x0 0x1000>,
1037 <0x0 0xfd4ab000 0x0 0x1000>,
1038 <0x0 0xfd4ac000 0x0 0x1000>;
1054 #size-cells = <0>;
1056 port@0 {
1057 reg = <0>;